strained silicon


June 20, 2014

14nm FD-SOI pushes strain and body bias for power savings

At the VLSI Technology Symposium a team led by STMicroelectronics described the techniques used for the upcoming 14nm FD-SOI to boost speed and density over the 28nm version.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , ,
March 19, 2013

FD-SOI costs to match bulk by year end, says ST

STMicroelectronics pushes on with FDSOI despite dissolution of ST-Ericcson joint venture that provided the lead customer for the process.
Article  |  Topics: Blog Topics, Conferences  |  Tags: , , , , , ,   |  Organizations: ,
December 10, 2012

Oxygen injection for go-faster 14nm transistors

Mears Technologies and UC Berkeley describe at IEDM 2012 how oxygen in a silicon superlattice could boost performance beyond strained silicon at 14nm.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: ,
December 10, 2012

Germanium finFETs, TFETs and MEMS modelled at IEDM

The modelling track at IEDM 2012 showed how germanium could be used in 14nm finFETs. Other work focused on tunnel FETs and analyzing MEMS using Spice.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , ,
October 15, 2012

FinFETs face planar fightback at IEDM

Advanced SOI devices with hybrid channel materials may challenge the finFET's future dominance, says IBM
Article  |  Topics: Commentary, Conferences, Blog - EDA  |  Tags: , , , , , ,   |  Organizations: ,
June 14, 2012

Strained silicon beats TSV stress in 3DICs

Texas Instruments had good news for teams that want to assemble 3DIC stacks using thru-silicon vias (TSVs). The stress induced by the copper TSVs is not as bad as many feared for nanometer-scale transistors.

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