Synopsys builds 3D into tool portfolio

By Chris Edwards |  1 Comment  |  Posted: March 26, 2012
Topics/Categories: Design to Silicon, Blog - EDA, - Product, Verification  |  Tags: , , , , ,

At the SNUG event this week, Synopsys is taking the wraps off its plans to support 3DIC, an area that is seeing a lot more public activity this month after Altera’s announcement of plans for work on heterogeneous interposer-based systems and Micron Technology’s work with others on hybrid memory cubes.

Marco Casale-Rossi, product marketing manager at Synopsys, said the company is working on the basis that there will probably be four dominant forms of 3DIC, each driven by different requirements. “The different flavors of 3DIC may emerge together but in different application segments,” he said.

The types include the two types of memory cube, 2.5D systems based on interposers favoured today by vendors such as Altera and Xilinx, and ultimately the mixed-technology stack in which the through-silicon vias are punched through logic and mixed-signal dice to form a highly compact system-in-package.

The last one is likely to come later because it puts the most stress on active circuits – each die carrying TSVs has to be thinned to tens of micrometres thick – and transistor characteristics can change dramatically with stress.

Stress is a bigger problem for mixed-signal circuitry than digital according to work carried out by IMEC and Synopsys. “The keep-out zone is ten times bigger than it would be for digital,” said Casale-Rossi. “Understanding these effects is fundamental to implementing EDA flows. For example, you need to tell the place-and-route tool which parts of the die are safe to use. And you have to be able extract the electrical characteristics of the TSV itself.”

That, in turn, increases the need to move to 3D parasitic extraction techniques, which is what has happened with StarRC, said Casale-Rossi. And that is not just for the ‘full’ 3DIC technologies. Similar to power semiconductors, interposers have features on both sides of very thin silicon.

“You need to extract all those 3D structures. We have upgraded our extraction technology to account for that,” Casale-Rossi claimed.

A further addition to the toolsuite is an update to IC Validator to perform layout-versus-schematic checks across circuits that span a stack of components. HSpice has also been upgraded to include models for work with 2.5D and 3D structures as well as with new commands to handle 3D circuits.

On the test side, Casale-Rossi, said: “New standards are emerging for the test of 3D structures, to test that the TSVs are working fine. You cannot access each layer from the outside, so more self-test and JTAG-based testing are needed to improve visibility for each tier. In memory stacks, the memories will not have embedded test structures, so you need test logic on the logic chip in the stack and then provide ways to access each tier at a time.”

Casale-Rossi said access to a wide portfolio of tools will provide an advantage “because 3DIC will bring together many technologies that were in the past completely separate”.

In the immediate future, with the exception of the memory stacks, which use TSV interconnects to massively increase bandwidth without driving up power, 2.5D is the likely answer for many people, said Casale-Rossi. “We see 2.5D as a very viable solution, even for people who not long ago were saying ‘3D, 3D, 3D’.”

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