Gold Standard Simulations (GSS) has launched a tool intended to help fabless chipmakers squeeze more out of existing processes rather than accept the risk and expense of moving to more advanced, finFET-based processes.
Design for the 20nm generation of processes has revealed power and clocking issues for the two major FPGA manufacturers presentations at Hot Chips revealed.
At the VLSI Technology Symposium a team led by STMicroelectronics described the techniques used for the upcoming 14nm FD-SOI to boost speed and density over the 28nm version.
Qualcomm will present at VLSI Technology Symposium 2014 a version of TSMC's 20nm technology that uses design and process tweaks to reduce the number of double-patterned layers.
But some research and process collaboration is set to continue in the background as Samsung, GlobalFoundries and IBM chart their own priorities.
Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.
TSMC stays the course with new co-CEOs as Morris Chang retains executive leadership for now while finFET, 3D and other new technologies settle in.
Research group CEA-Leti expects to have design kits ready for a 10nm FD-SOI process in June 2014
Cadence Design Systems has rolled out a new version of Virtuoso that deals with the physical-implementation issues that arise in the sub-28nm nodes.
Altera has disclosed a number of the features that will make it into the top end of its upcoming 'Generation 10' family of FPGAs.
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