Analog Bits

October 16, 2012

EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes

IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology

Article | Topics: Commentary, Conferences, Blog - EDA | Tags: 2.5DIC, 20nm, 3DIC, double patterning, dummy fill, extraction, foundry, Open Innovation Platform, reference flow | Organizations: Analog Bits, Cadence Design Systems, ITRI, Mentor Graphics, Synopsys, TSMC

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