Strained silicon beats TSV stress in 3DICs
Jeff West, a member of technical staff in interconnect process development at Texas Instruments, had good news for teams that want to assemble 3DIC stacks using thru-silicon vias (TSVs). The stress induced by the copper TSVs is not as bad as many feared for nanometer-scale transistors.
West described publicly for the first time at the VLSI Technology Symposium in Honolulu, Hawaii TI’s work on TSVs for logic – as opposed to analog and mixed-signal devices – and focused on the effects on 28nm-class devices, which already have plenty of stress imparted to them. The last thing you want is a nearby TSV reversing the beneficial effects of that stress and strain on performance.
The TI team created test structures that analyzed the impact on stress on devices that were placed at various points around a 10µm-diameter TSV made on a via-middle process. The devices used the standard  orientation: “Our poly[silicon] gate lines are always north-south,” said West.
From 40µm down to 4µm away from the TSV, the effect of TSV stress on the device was low for both NMOS and PMOS transistors. “The good news here is that you see very little shift: less than 2.2 per cent. When you compare that to other sources, such as dual-stress liner effects, which are in the 10 per cent range, length of diffusion at 8 per cent and well-proximity effects of 6 per cent, these are all much more significant that the TSV down to a distance of 4µm,” said West.
Raising the temperature to 105°C – the kind of local conditions that a mobile processor could encounter – altered the stress. “But the magnitude of the shift is small compared to other effects and the shift can take you the right way, closer to the original.”
One reason for the low apparent TSV stress is that, based on measurements that TI made, the effect is more pronounced deep into the wafer. The local strain enhancements used to push and pull on the PMOS and NMOS transistor channels has a more significant local impact. “We are creating local compresion under the Si. And we have shallow trench isolation oxide that is also compressive These tend to offset tensile stress from the TSV.”
Experiments by a team led by Professor Paul Ho of the University of Texas at Austin looking at piezoelectric effects on CMOS transistors backed up the TI findings for NMOS devices but differed on PMOS. However, the University of Texas simulations did not take into account deliberately introduced local strain.
“For n-type transistors, the two effects cancel each other out. It’s dependent on orientation but most devices use the  alignment and, on this, the NMOS effect is low. For p-type devices, the overall effect can be quite high: as much as 65 per cent,” said Ho.
The TI work is oriented toward use with wide-I/O memory interfaces. As a result, the I/O transistors that interface with the TSV-borne signals need to be placed behind ESD and decoupling capacitors.
“We have to put cells that don’t have transisters in them close to the TSVs anyway. People call them keepout zones, but we are putting things in those spaces anyway,” said West. The result, he claimed, is that transistors will not be closer to the TSV than 4µm in any case.
To stop the TSV from pulling so much that it forms pits or disrupts the fragile ultralow-k dielectric in the interconnect layers, the TI via is protected by a cap formed from metal one and two. Then a thin spine of vias and metal is placed over the cap that reaches to the stiffer TEOS layer at the surface.
West said this approach provides better interconnect density than a via-last technology: “The advantage of the spine is that it’s narrower than the TSV itself. Porosity blockage not as bad as if the TSV went all the way through the interconnect stack.”
West said TI said the company’s schedule for TSV-based devices is “in line with the projections of the various consulting agencies”.
Pingback: Semiconductor roadmap gets fuzzy at IEDM - Tech Design ForumTech Design Forums