It's time to act if you want your semiconductor device or process research to be considered for presentation at IEDM 2013 in Washington DC this December.
The International Electron Device Meeting takes place in San Francisco the week of 10 December 2012 and will, among many other things, focus on challenges for finFET-based processes as well as the issues for 14nm processes and beyond.
Can planar devices on fully depleted SOI resist the relentless rise of finFETs as the next device architecture of choice for the semiconductor industry? An evening panel at IEDM explored the trade-offs
Semiconductor process options outlined at IEDM by Luc van den Hove of imec as industry faces hard choices and rising costs
Mears Technologies and UC Berkeley describe at IEDM 2012 how oxygen in a silicon superlattice could boost performance beyond strained silicon at 14nm.
The modelling track at IEDM 2012 showed how germanium could be used in 14nm finFETs. Other work focused on tunnel FETs and analyzing MEMS using Spice.
finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
Ambipolar FETs, which can be n or p-type dependent on a control gate, could offer a new way to design circuits at 20nm and below.
Advanced SOI devices with hybrid channel materials may challenge the finFET's future dominance, says IBM
Intel finFET family grows to support SoC use, as TSMC boosts p-channel performance with germanium
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