Semiconductor roadmap gets fuzzier at IEDM

By Luke Collins |  No Comments  |  Posted: December 11, 2012
Topics/Categories: Conferences, Design to Silicon, Blog - EDA  |  Tags: , , , , , , , , , , , , , ,  | Organizations: , ,

The International Electron Devices Meeting usually provides a good opportunity to take stock of the status of the semiconductor process roadmap to date and the challenges the industry faces over the next two to three years. Luc van den Hove, CEO of imec, used his speech during the conference’s plenary session to do just that, pointing out which issues should be fairly straightforward to overcome and which could act as roadblocks to progress.

Imec’s More than Moore outlook means that van den Hove’s speeches are usually set in the context of a vision of electronics helping provide a better life for all, through everything from wearable health monitoring patches to always-on communications for our personal devices. These visions may come to pass or they may not: what they do offer is a useful context in which to look at the demands on traditional device scaling, as the industry wrestles with a much more uncertain technology roadmap than it has faced for years.

Van den Hove’s tour de horizon began with a look at current mainstream thinking at 22nm, where he sees the industry focusing on fully depleted devices, enabled either by putting the channel in a fin raised above the substrate or by building it on an insulating layer, with high K dielectrics and metal gates. These approaches provide better electrostatic control of the channel and so suppress the short-channel effects that have emerged now that device dimensions are so small.

The challenges for finFET (Guide) users, according to van den Hove, include achieving consistent conformal doping of the fin, patterning the gate over the fin shape, finding space between the base of the fins to include the channel stressors essential to increasing carrier mobility, and achieving consistent results with replacement metal gate processes that use atomic layer deposition.

Van den Hove says that the difficulty of applying strain to the channel of sub-14nm devices means that process architects will have to find new ways forward, increasing the drive current by using high-mobility materials such as germanium, to increase hole mobility, and III/V materials to increase electron mobility. These could be applied to devices built on bulk silicon or by using aspect ratio trapping in finFETs. Candidate materials for n-channel devices are InGaAs, and for pFETs, germanium.

Challenges in using these materials include process complexity, defect control, surface passivation, finding the right stressors, and contact formation for the III/V materials. But it’s a hopeful message overall: “this will take us at least to 10nm,” said van den Hove.

Beyond 10nm, he sees the need for new architectures, such as ‘gate all around’ devices, for which the challenge is making the contacts. The response is to turn finFETs from the horizontal to the vertical, so that they form nanowires that would offer strong electrostatic control of the channel and good contactability, and offer new circuit layouts that might also have area benefits.

The other option is tunnel FETs, which could be integrated into a vertical structure and offer useful device characteristics such as a steep subthreshold slope. The challenge with these devices is injecting enough drive current into them, so they need to be built with a low-bandgap material in the source, or with a greater tunnelling area. Ultimately, we may have to turn to carbon-based materials such as grapheme, or molybdenum sulphide, as one IEDM presentation will propose this week.

“We do have so many options to go down to dimensions that a few years ago we would not even have imagined,” said van den Hove, who pointed out that material and device innovations tend to take turns at keeping Moore’s Law on track.

Van den Hove also talked about the challenge of achieving the very high bandwidths between processor and memory that are necessary to achieve the kind of multimedia performance necessary in today’s portable devices, with 3D stacking (Guide) using through silicon vias (TSVs) and microbumps now being an accepted way forward. The challenges of this approach include integrating the TSVs through areas of dense circuitry, and avoiding the substrate distortions caused by the TSVs interfering with the sophisticated stressor mechanisms around the active devices – although this may not be as much of a problem as it seems.

In memories, van den Hove says flash scaling faces severe challenges, “but it is remarkable how this has been able to scale to the 1xnm node”. Beyond this, options to replace flash include 3D SONOS devices, and ReRAM. For DRAM, the continuing challenge is to scale the cells down by using higher K dielectric materials, although van den Hove predicts that ultimately, DRAM will be replaced by STT (spin transfer torque) RAM. In SRAMs, the challenge is process variability, with STT RAM also a candidate to eventually replace embedded SRAM.

The short-term fly in the ointment for the semiconductor industry is its failure to develop a next-generation lithography system to pattern the densest features of future device generations. Van den Hove says imec’s lithography research is showing some good results, with steppers being able to align one mask and the next in the same machine to within 1nm, and between one machine and another to within 5nm.

“The biggest challenge is still the power of the EUV sources, which are still not performing at the intensity levels we need,” said van den Hoe. “We believe the problems are not fundamental – they’re engineering problems  – but it is very challenging.”

Van den Hove says that a 193nm stepper with a 1.35 numerical aperture can pattern the finest features of a 20nm process using a lithography-aware layout and double patterning (Guide), but at 14nm companies will have to use costly triple-patterning techniques. The industry seems to be working hard to deal with the issue. Intel was at pains to show that it only used double patterning for the densest Metal 1 layer of its new 22nm SOC process, while IBM used lithography-aware masks and two orthogonal dipole illuminations to pattern the densest features of its latest process for making server and mainframe chips.

The more troubling issue is that the lack of adequate-power EUV sources is slowing down the advance to new process nodes.

“EUV is needed if you want to do a true 50% cell area reduction,” between one node and the next, according to van den Hove, and so it looks likely that 14nm design rules will have to be more relaxed than they would be if normal progress were possible.

The late arrival of EUV is also opening up opportunities for alternative techniques such as directed self assembly, in which two polymers dry to a series of lines and spaces whose pitch is defined by the length of one of the polymers. imec has already seen 12.5nm half-pitch patterns, but there are still problems to be overcome such as handling the ends of the lines, and making the cut mask which defines the pattern – for which you still need EUV lithography.

“These kinds of technologies are not a replacement for EUV, although they may delay its introduction by a generation,” said van den Hove.

“We do have a lot of options on the roadmap but the challenges are phenomenal. It will be even more important to bring together expertise and collaborate down the value chain to bring the kind of innovation we need,” said van den Hove. And he ended on a positive note, predicting that there is another ten years of semiconductor process development ahead.

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