substrate stress


June 18, 2017

TSMC encapsulates CoWoS for supersized SiP

TSMC encapsulated the multiple chips assembled on a 1200mm2 silicon substrate to cut the chance of damage from warping with the company's CoWoS2 SiP technology.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , ,   |  Organizations:
April 24, 2015

Do you need more stress (analysis) in your life?

Mentor Graphics is working on technology to analyse the effects of mechanical stress on integrated circuits, describing progress at the company's U2U conference.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations:
December 13, 2012

3D-IC integration prospects improving, say IEDM researchers

3D-IC integration techniques such as the use of TSVs, die stacking and interposers are unlikely to limit performance, according to research from TSMC and IBM
Article  |  Topics: Blog Topics, Conferences, Design to Silicon  |  Tags: , , , , , ,   |  Organizations: ,
December 11, 2012

Semiconductor roadmap gets fuzzier at IEDM

Semiconductor process options outlined at IEDM by Luc van den Hove of imec as industry faces hard choices and rising costs
June 14, 2012

Strained silicon beats TSV stress in 3DICs

Texas Instruments had good news for teams that want to assemble 3DIC stacks using thru-silicon vias (TSVs). The stress induced by the copper TSVs is not as bad as many feared for nanometer-scale transistors.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors