May 22, 2018
IEDM has issued a call for papers for its 2018 conference, expecting to cover devices and circuit interactions in neuromorphic, quantum and conventional computing.
April 10, 2018
Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.
October 18, 2017
Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December's IEDM.
June 18, 2017
TSMC encapsulated the multiple chips assembled on a 1200mm2 silicon substrate to cut the chance of damage from warping with the company's CoWoS2 SiP technology.
June 5, 2017
Mentor, a Siemens business, has formed an alliance with foundries and OSAT providers and launched a flow that brings IC and package design together.
May 30, 2017
Cadence Design Systems has brought its chip- and PCB-design environments closer together as the shift towards multichip packages gains pace.
May 19, 2017
Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing finFET designs to more than 100, according to Tom Beckley of Cadence.
January 9, 2017
Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits.
June 9, 2016
Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
March 31, 2016
The EDA Consortium is rebranding and extending its activities to better reflect all the tools and services that now comprise IC design.