Sub-10nm finFETs to feature at IEDM

By Chris Edwards |  No Comments  |  Posted: October 18, 2017
Topics/Categories: Blog - EDA  |  Tags: , , ,  | Organizations: , , ,

Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December’s International Electron Device Meeting (IEDM).

At the event, which runs from December 2-6, 2017 at the Hilton San Francisco Union Square Hotel, Intel engineers will describe their third mainstream finFET process: a 10nm logic platform that uses self-aligned quadruple patterning (SAQP) for critical layers. According to Intel, the 7nm-wide fins can be fabricated on a pitch of 34nm with a height of 46nm. The process provides drive currents that are 71 per cent and 35 per cent higher than the 14nm finFET platform for NMOS and PMOS transistors, respectively.

To try to improve interconnect resistance on a fine-pitch process, Intel has moved to cobalt wires for the lowest two layers, claiming an possible tenfold improvement in electromigration suppression and a halving of via resistance. The company expects to improve cell-area scaling by making it possible to form metal contacts over active gates instead of forcing the contacts away from the fins, the approach used on previous processes.

The 204Mbit SRAM test chip used to demonstrate the process’ viability has three memory cells that range in density from 0.0312µm2 to a fast design that takes up 0.0441µm2.

GlobalFoundries successor to 14nm is tagged as a 7nm process that uses SAQP for fin formation and SADP for metal layers. The company is claiming a minimum SRAM cell size of 0.0269µm2 and an improvement of 2.8x in routed-logic density versus the company’s 14nm process.

Looking further ahead, research institute Imec will describe its work on manufacturing devices using stacks of gate-all-around (GAA) nanowires – one of the options for post-finFET processes. The team has built the first working ring oscillators for a proof of concept. Another team from Imec has looked at aging mechanisms such as positive-bias temperature instability (PBTI), which appear to be similar to those for finFETs. However, self-heating in such highly constrained structures is likely to dominate the degradation effects.

Focusing on a move to the vertical dimension for further scaling, IBM will describe continuing work on its “electronic blood” concept, using cooling fluids to deliver power electrochemically instead of just using wires to circuits inside 3DICs.

CEA-Leti, through its work on CoolCube, continues to analyze thermal effects, using demonstrators that are assembled from 7nm-thick layers of silicon deposited on an SOI wafer. In the latest batch of results to be described at IEDM, the group has found the increase in a device’s channel temperature, captured using gate-resistance thermometry, matches values mathematically derived from the subthreshold slope – a result that should help with thermal modelling of stacked layers.

As well as logic scaling, the conference will cover a range of novel technology directions that include core components for biosensors, neuromorphic devices for AI, and silicon photonics.

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