FinFET-project growth ‘stunning’ says EDA exec

By Chris Edwards |  No Comments  |  Posted: May 19, 2017
Topics/Categories: Blog - EDA  |  Tags: , , , , ,  | Organizations:

Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing advanced-node designs, according to Tom Beckley, general manager of Cadence Design Systems’ custom-IC and PCB group.

The need for higher integration and performance is apparently driving a migration towards the finFET end of the process-node scale despite the higher engineering costs.

“The number of people doing advanced design is stunning to me,” Beckley said at the CDNLive EMEA conference in Munich, Germany this week (16 May). “Five years ago, I was asked how many would be doing a finFET design. I said a few dozen. I was wrong. More than 130 different companies are doing finFET designs, with thousands and thousands of users engaged. Why? Because of the opportunities we’ve been talking about.

“I was talking to one customer that has been working with 350nm. They are making the leap to 16nm. Why? They said they can’t keep operating in the old world,” Beckley added, pointing to markets such as automotive where new entrants are expecting to use more advanced processing arrays than incumbent suppliers.

Beckley cited numbers from Pacific Crest Securities claim strong growth in machine learning leading to the shipment of more than a billion units per year by 2025.

But 2D scaling has to run out of steam at some point, Beckley said. That calls for changes in what it means to be an chip designer. “We are looking at multidie, something exotic, or 3D scaling. Increasingly, wafer-scale packaging is moving into the domain of the IC designer. This is why we are trying to merge and bring information into the flow from packaging design. We are pulling in Allegro and Sigrity checks and pathfinding technology at the floorplanning level: how am I am going to optimally locate I/O locations?”

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