3DIC

Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits.

Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.

The EDA Consortium is rebranding and extending its activities to better reflect all the tools and services that now comprise IC design.

Following Mentor's acquisition of Tanner EDA, management expect the integration will help with a drive into IoT applications and systems that need to go beyond standard IC lithography.

Altera is using a combination of Intel's 14nm process technology and multidie packaging to boost the logic-cell count for its FPGAs, together with a superpipelining strategy to help balance area and clock speed.

Last week's announcement by Avago that it would buy Broadcom looks to be only partly about bulk. The merger could help drive SIP and 3DIC integration.

Mentor Graphics is working on technology to analyse the effects of mechanical stress on integrated circuits, describing progress at the company's U2U conference.

Flow draws on existing strengths in Xpedition, Valor, Nimbic and Flotherm among others to optimize 3D design projects and improve cross-disciplinary communication.

Foundry veteran Simon Yang told Semicon China while things are looking up the country cannot count on ‘traditional’ methods or advantages if it's to be a major chipmaker.

At IEDM 2014, CEA-Leti presented a technique that prevents damage to base-layer transistors in monolithic 3DIC processes. As work progresses, the institute is preparing to receive 3DIC designs in 2017.