Verification perspectives 2: formal for the masses and graph-based techniques
The second part of our interview with Mark Olen and Jim Kenney, looks at how formal and graph-based techniques move the market beyond simulation.
Author Archives: Paul Dempsey
Mentor targets 10X cut in reliability test for power electronics
New MicReD power tester identifies failure causes without the need for post-test lab analysis
Synopsys speeds HAPS prototyping with ProtoCompiler
HAPS-specific enhancements to Synplify and Certify join next gen partitioning and planning in suite that claims 3X boost in time-to-prototype
Verification perspectives: the growth of emulation
The first in a series of articles on how various vendors are addressing the flow's most challenging task looks at Mentor's strategy for emulation.
Common Platform foundry alliance to be wound down
But some research and process collaboration is set to continue in the background as Samsung, GlobalFoundries and IBM chart their own priorities.
Mentor builds simulation-emulation bridge to ‘Verification 3.0’
Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.
Mentor’s User2User Silicon Valley conference this week
Registration is free-of-charge to attend Mentor, Oracle and Samsung keynotes and choose from nine technical tracks at one-day event.
Intel and Altera extend foundry deal into interposer and full 3D
Deal quashes rumors that Altera was about to move its cutting edge production back to TSMC, but nor does it appear to be 'exclusive' for 3D products.
Mentor’s Valor tightens PCB design-to-manufacture links
Valor NPI-based flow claims first in automating the passage of drawings to fabrication, and enabling dynamic DFM feedback from manufacturers.
Real Intent’s Ascent XV at the ‘fuzzy’ boundary between design and verificiation
Upgrade to Ascent XV X-propagation and reset optimization tool claims 10X runtime gain, deeper reporting, further integration with Verdi and more.