Flow stability and chip reliability top the papers at DVCon Europe
The two best papers at the recent DVCon Europe underlined two of the issues that now face chip-implementation teams: efficient flows and reliability.
flow convergence
New flows needed for the ‘insects of the SoC world’
Chris Rowen, CTO of the IP group at Cadence Design Systems, expects the internet of things (IoT) to cause a split in approaches to SoC design, one of a set of predictions about the nascent market.
Real Intent’s Ascent XV at the ‘fuzzy’ boundary between design and verificiation
Upgrade to Ascent XV X-propagation and reset optimization tool claims 10X runtime gain, deeper reporting, further integration with Verdi and more.