transactors


February 3, 2015

Speeding up simulation using native System Verilog transactors

Partitioning a verification test bench using native System Verilog transactors can make it easier to move between simulation and emulation.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , ,   |  Organizations:
April 28, 2014

Synopsys speeds HAPS prototyping with ProtoCompiler

HAPS-specific enhancements to Synplify and Certify join next gen partitioning and planning in suite that claims 3X boost in time-to-prototype
Article  |  Topics: Blog Topics, RTL, Verification  |  Tags: , , , ,   |  Organizations:

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