Zero ASIC open sources system simulation/emulation platform
Start-up launches platform on path to the specification, emulation and simulation of large chiplet-based designs.
Author Archives: Paul Dempsey
Benchmarking the maturity of AI in EDA
Solido discusses how it has leveraged AI for SPICE level efficiency and the benchmarks it has used.
Tessent speeds ‘shift left’ drive for test at RTL
Tessent RTL Pro allows wrapper cells and x-bounding logic to be inserted earlier in designs.
Catch up with the state-of-the-art in ‘shift left’
Just how much of the flow has already has 'shift left' benefit and what is fueling further progress.
Cadence mixes know-how and AI to bridge RTL gap
The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.
Calibre ‘shifts left’ into place and route
Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R
Charting the path for machine learning in functional verification
A comprehensive review of ML's potential and its current use identifies challenges ahead.
Siemens harnesses machine learning for more comprehensive verification
As first silicon success declines, new software aims to provide a more holistic view of coverage data from multiple sources.
Identifying AI opportunities in PCB design
The key to exploiting AI is being clear about where its family of technologies can help to improve and democratize design.
Siemens automates test to handle multi-die 2.5D, 3D and 5.5D architectures
Tessent Multi-die extends the capabilities of the DFT suite in line with new standards intended to enable widespread adoption of interposer and stacked die strategies.