ANALYSIS: nVidia has the IP to license but what about the ecosystem?
To get others to adopt its GPU cores, Nvidia must quickly build partnerships with tool vendors and foundries that guarantee easy implementation.
Author Archives: Paul Dempsey
Real Intent highlights hierarchical clock domain crossing with Meridian 5.0
SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
Synopsys launches single kit to optimize IP across PPA
Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.
Mentor adds rapid RFQ to Capital suite
Wire harness margins are tight yet quotes still need to be turned on a dime. Integrating that process into existing tools aims to help.
Gartner: Multi-patterning here to stay, EUV lithography still 50:50
Plan around 193nm immersion lithography. Alternatives are years off and not guaranteed, says analyst group
DAC 2013 Preview VII: Verification and simulation
DAC 2013's technical program has four sessions on innovation for verification. Some of the hot topics being covered include 3DIC and analog.
Aldec automates safety-critical traceability
Spec-TRACER addresses stringent design reporting demands in safety-critical markets, some of which are moving into the mainstream.
DAC 2013: The Gary Smith EDA ‘what to see’ list is live
Whether your going to DAC 2013 or not, the EDA analyst's round-up is an invaluable guide to design trends and the tool vendors most actively addressing them.
Jasper adds low-power App to formal family
Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.
Forte Cynthesizer aims at performance, power and ease of use
The fifth generation of Forte Design System's Cynthesizer tool is a slice of system-level evangelism.