June 9, 2014
Can applications provide useful input for verification? They can but not when run straight out of the box, panelists at DAC 2014 said.
May 21, 2014
The second part of our interview with Mark Olen and Jim Kenney, looks at how formal and graph-based techniques move the market beyond simulation.
April 22, 2014
Cadence Design Systems has reached an agreement with Jasper Design Automation to buy the formal-verification specialist for $170m in cash.
April 7, 2014
The 51st Design Automation Conference, to be held in San Francisco in early June, is offering free exhibit floor entry for the full three days.
November 5, 2013
Jasper Design Automation has developed a tool that analyzes RTL and gate-level HDL for hidden paths that may expose on-chip secure elements to hackers.
October 11, 2013
The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.
October 9, 2013
The EDA vendor has set a broad agenda across two Silicon Valley events taking place in late October, with registration now open for both.
June 5, 2013
Deal creates methodologies and tools to help deliver IP and SoC assemblies verified using formal methods. Low-power verification strategy also launched.
May 14, 2013
Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.
May 14, 2013
Leaders from Cadence, Jasper, Mentor and Synopsys are late additions to DAC 2013, giving 15-minute pre-keynote talks previewing design's next half century.