partitioning


September 16, 2015

Synopsys extends FPGA-based prototyping to 1.6bn ASIC gates

Synopsys updates its FPGA-based prototyping system to offer more capacity, higher speed, faster bring-up, better ROI
Article  |  Topics: Blog - IP, - Verification  |  Tags: , , , ,   |  Organizations:
February 3, 2015

Speeding up simulation using native System Verilog transactors

Partitioning a verification test bench using native System Verilog transactors can make it easier to move between simulation and emulation.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , ,   |  Organizations:
April 28, 2014

Synopsys speeds HAPS prototyping with ProtoCompiler

HAPS-specific enhancements to Synplify and Certify join next gen partitioning and planning in suite that claims 3X boost in time-to-prototype
Article  |  Topics: Blog Topics, RTL, Verification  |  Tags: , , , ,   |  Organizations:
October 24, 2012

Tile-based integration of analog functions enables power controller family

Using a tile-based analog design methodology to produce power application controller ICs at Active-Semi
May 29, 2012

DAC 2012: Introducing Flexras Technologies

French start-up and conference debutant joins the drive to ease partitioning for FPGA prototypes
Article  |  Topics: Blog Topics, Verification  |  Tags: , , , ,   |  Organizations:

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