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May 14, 2021
How MaxLinear cut physical verification time with in-design DRC
A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.
Article | Topics:
DFM
,
Digital/analog implementation
,
Verification
| Tags:
design rule check
,
DRC
,
multi patterning
,
physical verification
,
pin assignment
,
place and route
,
via selection
| Organizations:
MaxLinear
,
Siemens EDA
April 28, 2014
Synopsys speeds HAPS prototyping with ProtoCompiler
HAPS-specific enhancements to Synplify and Certify join next gen partitioning and planning in suite that claims 3X boost in time-to-prototype
Article | Topics:
Blog Topics
,
RTL
,
Verification
| Tags:
debug
,
FPGA prototyping
,
partitioning
,
pin assignment
,
transactors
| Organizations:
Synopsys
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