DVCon Europe keynotes focus on connectivity
DVCon Europe's keynotes will examine verification issues in connected cars and 5G networks.
Author Archives: Chris Edwards
2D advances to take center stage at IEDM
At IEDM, TSMC is at the top of several papers that examine how 2D materials might be put into action as successors to silicon, alongside work from a variety of institutions on power integration and thermal management.
Nvidia proposes split-level link for chiplet interconnect
Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line.
Cadence extends AI to verification data with unified database
Cadence has brought the inputs for its AI-driven tools under the umbrella of a big-data collection platform and added functional verification to the list of products that use machine learning.
Intel and partners join for RISC-V development push
Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
Imperas releases RISC-V coverage library as open source
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
Accellera attempts to standardize CDC data
Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
Teledyne pushes for optical for remote RF heads
Teledyne e2v has demonstrated a prototype optical link that the company believes could replace electrical signaling for remote RF heads.
Open-source EDA grapples with the incentives issue
As the project that funded OpenRoad draws to a close, experts pondered its wider future at the 59th DAC.
‘Shocking’ quality sees vendors organize around RISC-V verification
Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.