Imec cleans up process for 2µm-pitch 3DIC stacks
Imec has developed cleaner techniques for preparing die-to-wafer bonding components for high-density logic-memory stacks and optical integration.
Author Archives: Chris Edwards
Dense packaging focus for ECTC
This year’s ECTC, held at the end of May, will continue its focus on the role of packaging in keeping silicon scaling on track.
VLSI to explore vertical device changes and 3nm finFET
The upcoming VLSI Symposium will examine progress in using backside contacts and 3D structures to improve density and speed as well as continuing improvements to finFET processes.
Arm embraces Transformers with faster NPU
Arm has launched what the company claims is its highest-performance and most-efficient AI accelerator.
Arteris extends safety and speed for NoC
Certification to ISO 26262 for automotive systems and compatibility with the latest Arm9 generation of processors and the CHI-E interface are among the updates to Arteris’ Ncore cache-coherent on-chip network IP framework.
Two projects to deliver digital twins for software-defined vehicles
Arm is working with Cadence and Siemens on separate projects to support its plans in the SDV space.
DVCon Europe calls for papers for 2024 event
DVCon Europe is looking for papers to be presented at this year’s event in mid-October.
Latest version of Verilog-AMS ready for release
The board of directors of Accellera Systems Initiative has approved the 2023 edition of the Verilog-AMS standard for release.
Cadence to work on IP for Intel 18A
Cadence has agreed to work with Intel Foundry Services on IP and flows for the 18A process, which will include backside power delivery and nanosheet transistors.
Accellera forms working group for mixed-signal interfaces
Accellera has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.