Author Archives: Chris Edwards

About Chris Edwards

Chris Edwards has spent a long time covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology. His work has appeared in a variety of international newspapers including The Guardian, The Daily Telegraph, The Age and the South China Morning Post.
July 22, 2021

Cadence uses reinforcement learning to tune flow

Cadence has launched a tool that the company claims can speed up implementation by applying machine learning across the flow.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
July 22, 2021

Arm shows off biggest flex processor so far

Arm and flexible-electronics specialist PragmatIC have demonstrated a 32bit processor implemented on a plastic substrate.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations:
July 19, 2021

Chiplet design raises big questions

Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , , ,   |  Organizations: , , ,
July 15, 2021

Chiplets to need digital twins for reliability

The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
July 14, 2021

Accellera approves IP security-documentation standard

Accellera has approved version 1.0 of the SA-EDI standard, intended to provide a consistent way of describing security concerns for IP cores.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:
June 17, 2021

Standard arrives for thermal simulation data

A de facto standard for exchanging thermal information about designs has become JEDEC standard JEP181.
June 16, 2021

Samsung moves further into 3D for denser flash

Samsung described at VLSI Symposia how it has used two further forms of stacking to increase flash capacity.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
June 15, 2021

Imec cuts transistor gap to less than 20nm with forksheets

Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
June 14, 2021

AI’s design speedups, with and without machine learning

At the VLSI Symposia, researchers described how AI hardware could help dramatically accelerate analog and digital design and not all of it directly through machine learning.
June 9, 2021

Xilinx retools Versal for high-end edge AI

Xilinx has reworked its Versal FPGA for edge-AI applications.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , , ,   |  Organizations: