Imperas and Synopsys team on RISC-V debug
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
Author Archives: Chris Edwards
Accellera forms CDC working group and takes security standard to IEEE
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
DVCon Europe best paper speeds up memory-controller tests
The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.
A*Star lays out SiP applications choices at IEDM
The choices for heterogeneous integration are falling into three main families, demonstrated by A*Star at IEDM 2022.
RISC-V gets verification and security IP additions
Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
Imec adds MOL layer to potentially cut cell size 20%
Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
Imec pushes endurance on ferro memory at IEDM
Imec has developed a high-endurance ferroelectric capacitor that could form the basis of storag-class embedded and standalone memories.
DVCon Europe looks to network effects
Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.
Real Intent tool looks for glitches
Real Intent has developed a tool to check design and the potential for circuits to glitch.
Semiwise brings cryogenic models to SOI
Semiwise has developed transistor models for the GlobalFoundries 22FDX that cover operation at cryogenic temperatures.