A*Star lays out SiP applications choices at IEDM
The choices for heterogeneous integration are falling into three main families, demonstrated by A*Star at IEDM 2022.
Author Archives: Chris Edwards
RISC-V gets verification and security IP additions
Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
Imec adds MOL layer to potentially cut cell size 20%
Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
Imec pushes endurance on ferro memory at IEDM
Imec has developed a high-endurance ferroelectric capacitor that could form the basis of storag-class embedded and standalone memories.
DVCon Europe looks to network effects
Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.
Real Intent tool looks for glitches
Real Intent has developed a tool to check design and the potential for circuits to glitch.
Semiwise brings cryogenic models to SOI
Semiwise has developed transistor models for the GlobalFoundries 22FDX that cover operation at cryogenic temperatures.
DVCon Europe keynotes focus on connectivity
DVCon Europe's keynotes will examine verification issues in connected cars and 5G networks.
2D advances to take center stage at IEDM
At IEDM, TSMC is at the top of several papers that examine how 2D materials might be put into action as successors to silicon, alongside work from a variety of institutions on power integration and thermal management.
Nvidia proposes split-level link for chiplet interconnect
Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line.