Cadence buys thermal software for data-center digital twins
Thermal-simulation specialist Future Facilities has agreed to be acquired by Cadence Design Systems.
Author Archives: Chris Edwards
Agile starts to build out analog portfolio with tool-based strategy
Agile Analog's oscillator IP sees the company focus on IP created with its own circuit creation and porting tool.
Fujimura asks EDA to bend towards manufacturability
Aki Fujimura of mask specialist D2S sees curved shapes as key to improving die yield and performance but it needs EDA support.
Fault simulator tackles intrusive hacks
Optima DA has turned its high-throughput fault-simulation technology to the checking protections against aggressive, intrusive hacks.
Siemens and Nvidia aim to bring more virtual reality to digital twins
Siemens and Nvidia have agreed to work more closely together to drive the development of higher-fidelity digital twins.
SoC project uses eFPGA to extend DSP instructions
R&D multicore processor demonstrates programmable extensions for DSP.
Aachen spinout claims fastest RISC-V simulator
MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.
Intel talks 4 at VLSI
Intel expects to double logic density through metal scaling and smaller cells with upcoming process.
3DIC design needs more hierarchy, TSMC says
TSMC calls for modular EDA flows and increased use of hierarchical verification to support complex 3DIC designs.
Real Intent updates reset and clock-domain crossing tools
Real Intent has upgraded its Meridian CDC clock-domain crossing sign-off tool, with support for multimode-aware dynamic models.