Accellera has published the version 1.0 draft of the proposed Security Annotation for Electronic Design Integration standard.
Author Archives: Chris Edwards
Siemens has introduced a cloud-based DFM tool intended to bridge the gap between the electronics design and manufacturing.
Cadence Design Systems has designed a new custom processor for the Z2 emulator and employed Xiliinx UltraScale+ for the prototyping platform.
Arm aims to introduce a novel security model in its upcoming v9 architecture along with further extensions for AI.
Imperas Software has released a free instruction set simulator that covers the OpenHW Group's implementations of the RISC-V processor architecture.
The best paper awards at this month's DVCon highlighted techniques to streamline verification. The European version in the meantime is looking for paper submissions.
IRPS will use a virtual format for its March conference and will take in the reliability of emerging as well as more established technologies.
Both Semicon West and DAC have been moved to December in anticipation of travel restrictions being much looser by then, with both events working on a hybrid physical and online format.
Yokogawa's development of a data-recording oscilloscope is built around the ability to connect instruments together and synchronize their measurements.
Pulsic has adopted the freemium approach with a tool that gives designers of analog circuits previews of how they will be implemented on-chip.