Imec pushes endurance on ferro memory at IEDM
Imec has developed a high-endurance ferroelectric capacitor that could form the basis of storag-class embedded and standalone memories.
Author Archives: Chris Edwards
DVCon Europe looks to network effects
Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.
Real Intent tool looks for glitches
Real Intent has developed a tool to check design and the potential for circuits to glitch.
Semiwise brings cryogenic models to SOI
Semiwise has developed transistor models for the GlobalFoundries 22FDX that cover operation at cryogenic temperatures.
DVCon Europe keynotes focus on connectivity
DVCon Europe's keynotes will examine verification issues in connected cars and 5G networks.
2D advances to take center stage at IEDM
At IEDM, TSMC is at the top of several papers that examine how 2D materials might be put into action as successors to silicon, alongside work from a variety of institutions on power integration and thermal management.
Nvidia proposes split-level link for chiplet interconnect
Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line.
Cadence extends AI to verification data with unified database
Cadence has brought the inputs for its AI-driven tools under the umbrella of a big-data collection platform and added functional verification to the list of products that use machine learning.
Intel and partners join for RISC-V development push
Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
Imperas releases RISC-V coverage library as open source
Imperas Software has published an open-source functional-coverage library for RISC-V cores.