3DIC design needs more hierarchy, TSMC says
TSMC calls for modular EDA flows and increased use of hierarchical verification to support complex 3DIC designs.
Author Archives: Chris Edwards
Real Intent updates reset and clock-domain crossing tools
Real Intent has upgraded its Meridian CDC clock-domain crossing sign-off tool, with support for multimode-aware dynamic models.
Cadence adds machine learning to electrical simulation
Cadence has used machine-learning techniques originally developed for its Cerebrus tool to build software that can speed up multiphysics analysis.
Oxide DRAM gains traction at VLSI Symposium
VLSI Symposium 2022 will show the rapid development taking place in oxide-based replacements for traditional DRAM cells as well as the emerging area of memory-based low-power machine learning.
Imagination brings in lower-cost access for accelerator IP
Imagination Technologies has dropped the requirement to take an upfront licence for some of its IP cores if customers join its Open Access program.
IEDM to celebrate 75 years of the transistor
Recognizing the 75th anniversary of the transistor in December, the 68th IEDM has taken on the theme of looking at “transformative devices to address global challenges”.
DAC returns to SF for in-person event
DAC returns to San Francisco in July for its 59th year as a purely in-person event.
Nvidia open to chiplet standards
Nvidia says it will support the UCIe chiplet interface standard once it has "stabilized" while opening up its latest form of NVLink to other companies.
Verification engineers look to better skills to beat schedules
A panel at DVCon argued too much of a focus on point tools coupled with challenges with interoperability and cross-industry cooperation is hindering the ability of SoC teams to design and verify complex products.
Synopsys talks AI in verification at DVCon
Synopsys R&D vice president Manish Pandey described the ways in which the tools supplier has harnessed machine learning so far to gain speedups and improvements in coverage.