Author Archives: Chris Edwards

About Chris Edwards

Chris Edwards has spent a long time covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology. His work has appeared in a variety of international newspapers including The Guardian, The Daily Telegraph, The Age and the South China Morning Post.
December 5, 2022

Imec pushes endurance on ferro memory at IEDM

Imec has developed a high-endurance ferroelectric capacitor that could form the basis of storag-class embedded and standalone memories.
Article  |  Topics: Blog - IP  |  Tags: , , , ,   |  Organizations:
November 21, 2022

DVCon Europe looks to network effects

Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.
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November 15, 2022

Real Intent tool looks for glitches

Real Intent has developed a tool to check design and the potential for circuits to glitch.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
November 14, 2022

Semiwise brings cryogenic models to SOI

Semiwise has developed transistor models for the GlobalFoundries 22FDX that cover operation at cryogenic temperatures.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: ,
October 25, 2022

DVCon Europe keynotes focus on connectivity

DVCon Europe's keynotes will examine verification issues in connected cars and 5G networks.
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October 17, 2022

2D advances to take center stage at IEDM

At IEDM, TSMC is at the top of several papers that examine how 2D materials might be put into action as successors to silicon, alongside work from a variety of institutions on power integration and thermal management.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , ,
September 21, 2022

Nvidia proposes split-level link for chiplet interconnect

Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line.
Article  |  Topics: Blog - IP  |  Tags: , , , , ,   |  Organizations:
September 15, 2022

Cadence extends AI to verification data with unified database

Cadence has brought the inputs for its AI-driven tools under the umbrella of a big-data collection platform and added functional verification to the list of products that use machine learning.
August 31, 2022

Intel and partners join for RISC-V development push

Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
August 3, 2022

Imperas releases RISC-V coverage library as open source

Imperas Software has published an open-source functional-coverage library for RISC-V cores.