Author Archives: Chris Edwards

About Chris Edwards

Chris Edwards has spent a long time covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology. His work has appeared in a variety of international newspapers including The Guardian, The Daily Telegraph, The Age and the South China Morning Post.
June 17, 2021

Standard arrives for thermal simulation data

A de facto standard for exchanging thermal information about designs has become JEDEC standard JEP181.
June 16, 2021

Samsung moves further into 3D for denser flash

Samsung described at VLSI Symposia how it has used two further forms of stacking to increase flash capacity.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
June 15, 2021

Imec cuts transistor gap to less than 20nm with forksheets

Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
June 14, 2021

AI’s design speedups, with and without machine learning

At the VLSI Symposia, researchers described how AI hardware could help dramatically accelerate analog and digital design and not all of it directly through machine learning.
June 9, 2021

Xilinx retools Versal for high-end edge AI

Xilinx has reworked its Versal FPGA for edge-AI applications.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , , ,   |  Organizations:
June 4, 2021

TSMC spins outs processes for automotive and RF

TSMC is developing processes for high-end automotive and RF based off its N5 and N7 families.
Article  |  Topics: Blog Topics  |  Tags: , , , , , ,   |  Organizations:
June 4, 2021

IEDM looks for papers across 2D devices to 3DICs

IEDM has issued a call for papers for what the organizers expect to be an in-person event in December.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,
June 3, 2021

Three libraries tune speed and density on TSMC’s 3nm process

TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations:
May 26, 2021

Arm rolls clickthrough license scheme into Flexible Access

Arm is reworking the DesignStart scheme it introduced several years, moving it under the umbrella of the broader Flexible Access program.
Article  |  Topics: Blog - IP  |  Tags: , , , ,   |  Organizations:
May 21, 2021

Cadence pushes its FastSpice to 32 cores

Cadence has launched a reworked FastSpice engine designed to split work across multiple cores more efficiently.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: