‘Shocking’ quality sees vendors organize around RISC-V verification
Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
instruction set architecture
Aachen spinout claims fastest RISC-V simulator
MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.
OpenHW gets free simulator from Imperas
Imperas Software has released a free instruction set simulator that covers the OpenHW Group's implementations of the RISC-V processor architecture.
Open and proprietary verification tools home in on RISC-V core quality
DAC provided a forum for the growing number of verification efforts focused on checking the architectural compliance and overall RTL quality of RISC-V processors.
Arm to let customers bolt instructions onto V8 processors
Arm has relented on its opposition to custom instructions with the decision to let customers add them to V8-M processors.
GSA on how to reinvigorate silicon business models
Open-source hardware, in-field configurability, and a hardware-plus-services approach could protect margins as the IoT hammers down costs, says GSA report.
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