‘Two wafers are better than one’ for 3D flash
Western Digital's head of technology set out at the recent VLSI Symposium the ways in which flash makers can scale without costs accelerating.
Author Archives: Chris Edwards
AI’s possible roles in verification covered at VF2023
The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.
UK consortium tapes out cryo-SRAM
A UK cryogenic-CMOS research project has taped out its first demonstrator chip for core memory IP expected to be able to operate at close to absolute zero.
Co-design underpins infrastructure acceleration at Google
At the recent VLSI Symposium, Google vice president Parthasarathy Ranganathan described the importance of co-design and the software stack in its data-center designs.
Air-filled waveguides to cut losses in mass-market radar
AT&S and Imec partnered to develop a way of putting low-loss waveguides into conventional PCBs to support D-band automotive radar and 6G modules.
Semidynamics adds flexible vectors to RISC-V cores
Semidynamics has released a customizable vector unit with out-of-order execution support to accompany its 64bit RISC-V processor cores.
X-Fab introduces BCD-on-SOI at 110nm
X-Fab Silicon Foundries claims to be the first with a foundry offering for 110nm BCD-on-SOI technology, aimed primarily at automotive designers.
UK projects builds models for quantum computer controls
Partners in the UK’s CryoCMOS Consortium have developed models that are expected to help deliver CMOS chips that will work inside cryostats.
Semidynamics pushes configurability on RISC-V core for HPC
Processor IP company will incorporate custom instructions and other changes in its superscalar core, which includes a novel memory unit for sparse matrices.
DVCon Europe adds research track
DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.