Codasip pips Arm to commercial CHERI with RISC-V version
Codasip has put support for a set of instruction extensions intended to secure memory into its RISC-V core designs.
Author Archives: Chris Edwards
X-Fab adds galvanic isolation to CMOS process
X-Fab has made it possible to put galvanic isolation based on capacitive coupling directly into chips made on its XA035 process.
Companies partner for embeddable ReRAM
SureCore and Intrinsic have teamed up to provide a way to implement resistive random-access memory as an SoC-embeddable technology.
Accellera publishes draft of CDC standard
Accellera has published for public review version 0.1 of a standard designed to help pass clock-domain crossing information between EDA tools.
Image sensors shrink at IEDM
This year’s IEDM features a number of papers that seek to drive down the size and boost the performance of image sensors.
Accellera updates portable stimulus standard
Accellera ’s board of directors has approved the version 2.1 of the Portable Test and Stimulus Standard.
Fast instruction simulator expands to Arm
MachineWare has expanded its portfolio of high-speed instruction-set simulators to the Arm Cortex-A and -M architectures.
Vertical integration expands at IEDM
Vertical integration is one of the major focus areas at the upcoming IEDM conference, both in terms of transistors and the multiple channels that will go into them.
Siemens and CEA link up on AI-assisted digital twins
Siemens and CEA-List have signed a deal under which the two organisations will research the combination of digital-twin and AI.
AI aims to cut CAD-model generation time
Ultra Librarian has developed an AI-driven CAD modeling engine that should slash the the time it takes to build component and subsystem models for PCB layout and system design.