Intel Foundry Services has signed a deal with Arm that will see the two companies work on a program of system and design-technology co-optimization.
Author Archives: Chris Edwards
Cadence Design Systems has expanded its use of machine learning for EDA into PCB design, joining a growing number of suppliers who have decided it is a sector that needs the AI treatment.
Nvidia's move into software aimed at mask production and EDA looks to be part of a wider shift to improve yields.
SEMI predicts 300mm capacity to grow to almost 10,000 wafers per month in 2026, up from 6,500 in 2021.
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.
The choices for heterogeneous integration are falling into three main families, demonstrated by A*Star at IEDM 2022.
Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.