Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.
Author Archives: Chris Edwards
At the VLSI Symposia, researchers described how AI hardware could help dramatically accelerate analog and digital design and not all of it directly through machine learning.
Xilinx has reworked its Versal FPGA for edge-AI applications.
TSMC is developing processes for high-end automotive and RF based off its N5 and N7 families.
IEDM has issued a call for papers for what the organizers expect to be an in-person event in December.
TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.
Arm is reworking the DesignStart scheme it introduced several years, moving it under the umbrella of the broader Flexible Access program.
Cadence has launched a reworked FastSpice engine designed to split work across multiple cores more efficiently.
Unisantis aims to use its vertical transistor design in a novel form of DRAM that could improve density four-fold.
Sigasi aims to attract developers working on open-source projects with a version of its Studio suite the company is making available for free to that community.