EDA

September 5, 2022

Parasitic extraction challenges intensify for 5G

5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.
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September 5, 2022

Cybersecurity must be built in not bolted on

Learn how one of the leading tool vendors addresses the security of its products and customer data through a ground-up cybersecurity strategy.
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August 31, 2022

Intel and partners join for RISC-V development push

Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
August 3, 2022

Imperas releases RISC-V coverage library as open source

Imperas Software has published an open-source functional-coverage library for RISC-V cores.
August 3, 2022

Accellera attempts to standardize CDC data

Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
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July 18, 2022

Open-source EDA grapples with the incentives issue

As the project that funded OpenRoad draws to a close, experts pondered its wider future at the 59th DAC.
July 14, 2022

‘Shocking’ quality sees vendors organize around RISC-V verification

Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
July 13, 2022

Siemens pushes DRC to the left

Siemens has launched Calibre DRC engines that make it easier to perform useful checks early in the layout process.
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July 12, 2022

Devgan plans for optimization through machine learning

Cadence president expects expanded role for reinforcement learning in tool portfolio and looks for help on AI for verification.
July 12, 2022

Siemens compiles analog into simulation for faster debug

Siemens EDA has launched a second version of its Symphony simulation environment designed to support quicker debug cycles.
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