Siemens pushes DRC to the left
Siemens Digital Industries Software has expanded its Calibre lineup for design-rule and manufacturability checks with a version of the engine that makes it easier to perform useful checks early in the layout process and reduce the time often needed just before tapeout to fix major issues.
This approach to “shift left” does not necessarily mean attempting to do everything> DRC-related early. Siemens argues that running design-rule checks tuned for signoff at early stage can harm overall productivity although it might cut some time towards the end of the project. The checks that run may flag up hundreds of errors that are mostly false alarms. They only appear because components that would correct them have not been added to the design because they are late-stage additions or will be fixed once neighboring blocks are in place.
Another issue is using truncated rule decks that just look for a subset of problems or which have not been verified by the target foundry. This can often happen in custom-design tools, Siemens argues, where the rules have been implemented directly in the layout tool rather than a dedicated DRC engine.
What Siemens says it has done with the Calibre nmPlatform’s RealTime Custom and Digital tools is to subdivide the catalog of DRCs into those that work for specific early layout tasks, including those that focus on netlist-, macro-, or IP block-level layout. Later layout modification, such as fill insertion performed by Calibre, can be back-annotated in the design database once they have been done.
The Calibre RealTime interfaces provide direct calls from layout software to Calibre analysis engines running the full foundry-qualified signoff Calibre rule decks. The nmDRC-Recon use-model in Calibre RealTime Digital already provides automated analysis of immature and incomplete designs across blocks, macros, and full-chip layouts and is tuned to find and fix high-impact physical layout earlier in the design and verification flow. In addition, Siemens has added the ability to flexibly to mark or “grey-box” immature cells and blocks but still check DRC against for issues that may already be apparent with adjacent blocks or upper-level metal. The company claims this ability helps supress nuisance DRC errors and can result in up to 50 per cent faster runtimes compared to nmDRC-Recon alone.
Calibre RealTime Digital also enables in-design fill using Calibre Yield Enhancer SmartFill as the engine, so that designers can get foundry-ready signoff fill from within their design cockpit.
The Calibre nmLVS-Recon module provides automated circuit verification of immature and incomplete designs, making it easier to perform short isolation (SI) analysis to identify possible circuit errors. This engine does not require changes to design inputs or foundry rule decks: it executes only the short isolation step of Calibre nmLVS. This can speed up LVS execution by up to 30x, allowing designers to complete several iterations in a day whereas, previously, this might be an overnight execution.
Calibre RealTime Custom has added the ability to automatically track DRCs across multiple regions to enable multiple edits to be fixed, tracked and checked simultaneously
