3D-IC integration prospects improving, say IEDM researchers
3D-IC integration techniques such as the use of TSVs, die stacking and interposers are unlikely to limit performance, according to research from TSMC and IBM
TSMC
EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
Intel, TSMC finFETs to star at IEDM
Intel finFET family grows to support SoC use, as TSMC boosts p-channel performance with germanium
TSMC updates reference flows for 20nm and CoWoS
TSMC has released two reference flows – one for its 20nm and the other for the form of 3D integration favored by the Taiwanese foundry, chip on wafer on substrate (CoWoS).
Event alert: TSMC Open Innovation Platform
With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.
IEF: Achronix plans embedded FPGA push
Achronix plans to use the FPGA fabric that it has developed for standalone products to be fabbed through Intel as the springboard for an embedded-FPGA offering.
TSMC joins Intel as ASML investor to accelerate availability of EUV, 450mm lithography
TSMC follows Intel in taking a stake in ASML to accelerate development of EUV and 450mm lithography equipment.
Aart de Geus on the changing face of EDA
The president and co-CEO of Synopsys provides his take on the mounting influence of software and physical effects in the creation of SoCs.
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