MRAM pushes speed and endurance at IEDM

By Chris Edwards |  No Comments  |  Posted: January 10, 2020
Topics/Categories: Blog - IP  |  Tags: , , ,  | Organizations: , , ,

Although it is a strong contender to replace flash as a non-volatile memory for SoCs, a problem for magnetic memory (MRAM) lies in its tradeoffs: you can have a memory cell that holds data long periods or you can have one that is fast, but not both at the same time. In one paper at IEDM late last year, Samsung engineers argued these tradeoffs can be supported within devices by targeting different onchip arrays with different levels of processing. It is a technique they call non-volatility modulation.

Using data from bake tests for different magnetic tunnel junction (MTJ) stacks, the team identified a strongly linear relationship between the junction’s switching current and the maximum temperature at which ten-year retention could be demonstrated. One way to leverage that is to create memory macros with cells of different sizes, with the large-cell arrays used to support high-retention requirements. The issue with that it is an approach that is broadly incompatible with modern patterning techniques where critical dimensions need to be kept consistent across the die.

So, the team turned to the alternative approach of tuning the perpendicular magnetic anisotropy (PMA) through small deposition and processing changes, which the company has not disclosed. The difference in PMA leads to changes in the switching energy and the retention of the target array. The team claimed the modulation does not adversely affect the distribution of switching currents within arrays and so eat into write margins.

Retention push

Other papers at the December conference demonstrated how MRAM is reaching maturity, particularly on the FD-SOI nodes. Another Samsung team described their tests on a 1Gbit spin-torque transfer (STT) MRAM aimed at the company’s 28nm FD-SOI node. According to the engineers, the array achieved a yield of more than 90 per cent, assisted with an error-correction scheme, and could demonstrate ten-year data retention at up to 105°C.

GlobalFoundries chose the 22nm FD-SOI node for its 40Mbit embedded MRAM array, with a target of meeting the industrial temperature range of -40 to +125°C and with improved tolerance to manufacturing processes like solder reflow. They pushed the test arrays through five solder reflow steps and tested the raw error rate, passing the 1ppm criterion they set. Like Samsung, the team augmented the array with error correction to help improve overall yield and reliability. With a focus on industrial applications another test was of endurance in a magnetic field. Projections showed the contents would survive ten years at 105°C in a 500Oe field.

TSMC took a similar approach for a 22nm CMOS array also intended for industrial applications, opting for an in-package shield to protect the memory from large external magnetic fields. Demonstrating one of the many tradeoffs of MRAM design, solder-reflow endurance could be exchanged for higher read and write performance.

Need for speed

Intel went in the opposite direction with a 2Mbit macro intended to serve as a component for level-four caches in high-speed computers. As a result, they focused density and speed on a memory cell that would use finFET transistors. For this application, retention could be scaled back to just a second with the help of a DRAM-like scrubbing operation. However, write endurance needed to be pushed to more than 1012, which placed limits on current on top of those implied by a small feature size. One helping hand for such a memory is that writing is easier at higher temperatures, which makes it possible to scale the voltage down: something the team took advantage of.

The IBM-Samsung MRAM Alliance also focused on last-level cache applications with a cell that can support write times down to 2ns thanks to change in the materials used to implement the free layers of the MTJ. This compares to 20ns for the Intel macro, which can support 4ns read accesses. A former stumbling block with making fast memories is that the precessional layer which drives fast writes much more than the thermal layer demonstrates a large, potentially damaging current spike. The team found a change in materials could remove this current surge and support fast writes with greater reliability.

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