TSMC

AMD used Calibre with optimisations implemented for cloud support to slash runtimes on high-end server processor designs.

Large-scale MCMs and novel device architectures bookend the papers on machine learning at VLSI Symposia in an event that will also cover chiplet integration and other topics.

Mentor's technical conference will take place on May 2 at the Santa Clara Marriott and feature more than 45 user and vendor presentations.

Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services (AWS) or Microsoft Azure.

DAC 2018 will see Synopsys focusing on close links with foundry partners, as well as exploring ways to exploit the potential of machine learning, in both SoC architectures and SoC design flows.

New flow enables high-performance, high-integration designs.

LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.

ARM, Xilinx, Cadence Design Systems, and TSMC have agreed to produce a test chip for the CCIX project.

TSMC encapsulated the multiple chips assembled on a 1200mm2 silicon substrate to cut the chance of damage from warping with the company's CoWoS2 SiP technology.

Synopsys has released details on its varied activities at DAC 2017, ranging from panels to technical papers.