TSMC

June 6, 2019

Calibre scales to 4000 nodes for faster sign off in the cloud

AMD used Calibre with optimisations implemented for cloud support to slash runtimes on high-end server processor designs.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: , , ,
April 22, 2019

Machine learning and chiplets headline VLSI Symposia

Large-scale MCMs and novel device architectures bookend the papers on machine learning at VLSI Symposia in an event that will also cover chiplet integration and other topics.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: , ,
April 18, 2019

User2User Silicon Valley is two weeks away

Mentor's technical conference will take place on May 2 at the Santa Clara Marriott and feature more than 45 user and vendor presentations.
October 9, 2018

Synopsys takes TSMC design into the cloud; IP to 7nm, 5nm and automotive processes

Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services (AWS) or Microsoft Azure.
Article  |  Topics: Design to Silicon, Blog - EDA, IP, - Verification  |  Tags: , ,   |  Organizations: , ,
June 18, 2018

DAC 2018 preview: Synopsys

DAC 2018 will see Synopsys focusing on close links with foundry partners, as well as exploring ways to exploit the potential of machine learning, in both SoC architectures and SoC design flows.
Article  |  Topics: Conferences  |  Tags:   |  Organizations: , , , , , ,
May 2, 2018

TSMC certifies Synopsys tool flow for 7nm EUV process

New flow enables high-performance, high-integration designs.
Article  |  Topics: Blog - EDA, - Product  |  Tags: , ,   |  Organizations: ,
March 23, 2018

Layout schema generation speeds early-stage yield learning

LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.
September 12, 2017

Group to build CCIX accelerator test chip

ARM, Xilinx, Cadence Design Systems, and TSMC have agreed to produce a test chip for the CCIX project.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , , ,
June 18, 2017

TSMC encapsulates CoWoS for supersized SiP

TSMC encapsulated the multiple chips assembled on a 1200mm2 silicon substrate to cut the chance of damage from warping with the company's CoWoS2 SiP technology.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , ,   |  Organizations:
June 1, 2017

DAC 2017 preview: Synopsys

Synopsys has released details on its varied activities at DAC 2017, ranging from panels to technical papers.
Article  |  Topics: Conferences  |  Tags:   |  Organizations: , , , , , ,

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