The semiconductor industry’s half-century record of delivering increased functional integration relies upon the ability of design engineers to use the extra transistors that process engineers squeeze onto a die each year. But it is becoming more complex and costly to use the latest processes, a trend that threatens the flow of benefits from the constant doubling of functional integration predicted by Moore’s Law.
Back in 2004, a memorable keynote at the Napa KGD Packaging & Test Workshop, entitled “Much More than Moore”, proposed that “more than Moore”, that is, the 3D integration of complete, heterogeneous systems in the same package, is complementary to silicon-level integration, which is ruled by the well-known and established “more of Moore”. The presentation went on to suggest that the final result of combining “more than Moore” and “more of Moore” is surprisingly more advanced than what is allowed by the simple progression of the semiconductor roadmap through scaling. Today, some companies are wondering whether “more than Moore” may represent a technically and economically viable alternative to scaling: others believe that it may complement scaling to boost integration and performance to unprecedented levels.
Why 3D now?
Why do we need a three-dimensional (3D) integration scheme now, rather than back in 1958 when Walter Shockley patented one of its key elements, the through-silicon via (TSV)? The answer is fivefold.
First, using leading-edge 2DIC integration now only makes sense for the highest-margin, highest-volume designs. Unless you are going to be using millions of units, simply getting your design through the increasingly complex product qualification stage may provide you with more good die than you will ever need. Even if you were prepared to pay the premium to fabricate a small volume on a leading-edge process, you might not find a foundry to take on your design. According to an analysis by IBS, whereas a foundry was able to handle 60 to 80 new designs in the first year of offering its 65nm process, it may only be able to handle 12 to 16 designs in the first year of offering its 20nm process.
Second, our ability to handle large amounts of multimedia data is being threatened by bandwidth limitations between packaged processors and memory. Demand for bandwidth is doubling every three years, and although IC density doubles every two years, packaged I/O bandwidth is not keeping pace. In fact, the number of available I/Os per million transistors is steadily declining.
Third, we could build all sorts of interesting new classes of products if we had a good way to integrate digital CMOS with technologies such as RF, MEMS, and optoelectronics.
Fourth, power management is always an issue in modern systems design, and 3D integration can help with that, by shortening interconnects among the different die which, in turn, would reduce the need for global signal repeaters.
And fifth, the yield of large die on leading-edge processes is usually lower than on more mature processes. Integrating several smaller, high-yielding die on a substrate using 3D techniques may offer a higher aggregate yield than putting all the functions on one large die.
3D integration technologies
What are the basics of 3D integration? Tech Design Forum has covered this issue in detail in its Guide, but to recap: a 2.5DIC process interconnects bare die that are laid out, usually side-by-side, on a silicon interposer (think of a very large IC with the usual metal stack but no active logic). The silicon interposer routes the communication of the die with the package using vias that connect the microbumps on the top surface with the C4 bumps on the bottom surface.
In a 3DIC, on the other hand, die are stacked on top of each other and interconnected by vias that go right through their substrates and connect with bumps on the surface of the next die down; the lowest die routes all the communication with the package – for itself as well as for the upper die. There are various combinations of these approaches, with some describing the use of a 3DIC stack, for example of memory die, alongside other die mounted on a silicon interposer as a 5.5DIC.
So what can we build with 2.5DIC and 5.5DIC technologies? Samsung has already described a ‘memory cube’, in which multiple identical memory die are stacked and interconnected with TSVs. Micron has built a ‘hybrid memory cube’, in which identical memory die are stacked on top of a logic die that takes over all the memory controller functions, enabling both types of die to be built in optimized processes.
Xilinx has shown the heterogeneous integration of FPGA die and 28Gbit/s SerDes interface chips on a silicon interposer built in a 65nm process. Xilinx is using three or four smaller FPGA die rather than one huge one to improve its systemic yield, performance, and power, with the interposer providing around 10,000 interconnections between the FPGA die to mimic the connectivity possible in a monolithic solution. Options for a silicon photonic interface to complement the SerDes are said to be being explored.
ST-Ericsson has showcased the architectural flexibility that 3D integration enables by rethinking the way it puts together a processor and its memory. It has designed an application processor to access large amounts of memory through a very wide bus in the center of the chip layout, and mounted a memory cube with a matching wide I/O structure on top. The resultant 3DIC delivers a dramatic increase in bandwidth.
3DIC techniques may also enable more complex integrations, such as of multi-axis accelerometers, gyroscopes, and microphones for smartphones, or gyroscopes, accelerometers and logic for fashionable, wearable helmet airbag systems. The richness of options also means that designs can evolve along an integration path from, for example, a processor, MEMS die and RF chip on a PCB, to a 2.5DIC integration and finally to a full 3DIC implementation in which the functionality is repartitioned among the various die for greater efficiency.
The 3DIC EDA tool challenge
That’s the promise of 3D integration. The challenge for EDA tool-makers is to make the techniques accessible to those who want or need to use them to gain the advantage of “more than Moore” integration. Tool chains are being updated to handle complex issues such as the modeling and impact of 3D structures such as TSVs and microbumps on nearby active circuit areas, RC extraction in a 3D context, multi-technology SPICE simulation, DFT in a 3D context, multi-die and multi-technology static timing analysis and physical verification, non-Manhattan routing for the dense I/O redistribution layers, and so on.
Moving forward, there is much more to 3DIC than just implementation or verification, and we believe there are many more opportunities to extend the traditional EDA solutions to support this emerging technology. For example, virtual and fast prototyping is ideal for highly heterogeneous systems such as 3DIC; thermo-electromechanical simulation is also critical, and TCAD – while originally meant for process technology development – is an extremely powerful technology for modeling the thermo-electromechanical effects introduced by 3D structures.
Longer term, we wil need pathfinding tools that can deal with the cost, performance, manufacturing, thermal, and test trade-offs, and help to assess whether a system-on-chip (SoC), a system-in-package (SiP) or one of the many flavors of 3DIC integration is the most appropriate solution.
With planar integration becoming increasingly difficult, exclusive and expensive, 3D strategies open up a rich alternative vein of opportunity for increasing functional integration – with all the benefits that has brought over the past half century. We might even say that moving forward with “more of Moore” requires “more than Moore”!