Cadence has built a unified database to support a group of tools to support the planning and implementation of 3DIC designs.
IC Manage is expanding its work on big data in EDA with the creation of a labs program that aims to work with clients on novel ideas for analyzing the gigabytes of output from chip-design tools.
Ausdia has launched a product intended to reconcile the multiple sets of timing constraints needed for operating and test modes so that a consistent group of constraints can be fed to implementation tools.
Cadence Design Systems has developed a visual timing analyzer for Allegro that tunes signals used by high-speed protocols such as DDR4, PCI Express, and SATA.
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