December 18, 2019
Case study describes how RF/AMS specialist used Calibre RealTime Digital within its flow for a high-end DSP SoC.
August 27, 2019
The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.
August 15, 2019
A new whitepaper describes some of the techniques you can use to get the most out of cloud-based DRC with Calibre.
January 21, 2019
Physical verification challenge of large SoCs on leading-edge processes detailed in video series
November 14, 2018
Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
June 19, 2018
Early users of the new P&R integrated physical verification tool say time-to-sign-off was cut by 40% and above.
April 12, 2017
Cadence Design Systems has launched a design-rule checking engine that can distribute its workload across multiple servers in a cloud, private farm or mixture of both to speed up signoff.
January 17, 2017
DesignCon 2017 takes place from Jan 31 to Feb 2 at the Santa Clara Convention Center with its usual focus on PCB design and implementation.
March 24, 2015
Flow draws on existing strengths in Xpedition, Valor, Nimbic and Flotherm among others to optimize 3D design projects and improve cross-disciplinary communication.
June 4, 2012
The Silicon Integration Initiative (Si2) is targeting the end of the year for release 2.0 of its OpenDFM standard, which will include support for DRC+ and make it possible to build search engines for yield.