A quick and easy way to calculate P2P resistance and current density

By Li Li |  No Comments  |  Posted: May 10, 2022
Topics/Categories: EDA - DFM, Verification  |  Tags: , , , , , , , ,  | Organizations:

Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.

Some IC layout quality issues are harder to check than others. For example, when an analog block or an intellectual property (IP) cell is placed in a chip, the cell should have strong connections to power, ground, and other signal nets. The connection is considered robust if the point-to-point (P2P) resistance is small enough. A P2P resistance calculation is typically used to check this kind of issue. However, most existing P2P and current density (CD) checks are device-based or cell-based. Both of these often require a custom rule deck.

P2P and CD checking are normally used during electrostatic discharge (ESD) verification to determine whether an ESD discharge path is sufficiently robust and efficient. A typical ESD path might run from an I/O pad to a cluster of ESD devices, then to a cluster of power clamping devices, and end at one power or ground pad (Figure 1). To ensure the ESD path functions as designed, designers must examine not only the placement of the ESD circuits, but also the effective resistance values along each ESD path. If the interconnect along an ESD path has a high effective resistance, the ESD path becomes ineffective. Instead of diverting any ESD surge through the designed ESD discharge path, the ESD path will fail to protect internal function circuits from this current. This will leave them vulnerable to damage from an ESD surge [1].

Figure 1. An ESD protection path, showing an ESD surge (yellow) being diverted from design circuitry (blue) (Siemens EDA)

Figure 1. An ESD protection path, showing an ESD surge (yellow) being diverted from design circuitry (blue) (Siemens EDA)

Many foundries provide Calibre PERC rule decks that enable designers to run checks directly with the tool’s main deck, its layout vs. schematic (LVS) rule deck, and resistance/capacitance (RC) or R-only rule files. However, standard decks often do not cover all the ESD devices or paths that a designer may wish to inspect. So custom rule decks must be built.

Moreover, IC design houses develop their own Calibre PERC rule decks to check proprietary ESD structures and run custom checks. A deck’s author must understand both ESD structures and the syntax of the Calibre PERC platform to create accurate device-based P2P and CD checks. Creating and verifying these additional decks also requires time and engineering resources.

Often though, before running full-chip verification, designers just want to calculate P2P or CD between any two coordinate points of a net in the layout. The net may or may not be an ESD-related net. The start/end point may or may not be a device/cell pin. For example, when an intellectual property (IP) cell is placed in a chip, design teams simply want to check if the IP has robust connections to power, ground and other signal nets before running specific ESD checks on the full-chip layout. Or perhaps a group of nets must be checked to ensure they are the same length from one cell to another.

Coordinate-based checking

For quick layout verification runs like these, engineers not want to write a custom rule deck to define devices or cells. A new option eliminates the need for such custom decks.

Coordinate-based checks provide a faster and simpler method of running P2P and CD checks, without having to define complex devices, cells, or nets. In coordinate-based P2P and CD checking, coordinates are used to define a start/end location anywhere on a net. Design teams only need to input the desired coordinates and the corresponding conductor layers (layer name). LVS device extraction can be disabled in coordinate-based checks, and only polygons in interconnect layers need to be extracted, allowing coordinate-based checks to run very quickly.

The Calibre PERC reliability platform provides coordinate-based checks for logic-driven layout (LDL) CD and P2P resistance calculations. In the coordinate-based P2P checks, coordinates and layer names are called probe points, and are defined in a probe-mapping file that can be created manually in a simple ASCII format. The path name of this probe-mapping file is specified in the foundry Calibre PERC rule deck. Creating a probe mapping file is fast and easy, and the Calibre PERC rule deck modifications are limited, making it simple to start using coordinate-based P2P and CD checks quickly.

Figure 2 shows a set of coordinate-based P2P check results displayed in the Calibre RVE results viewer. Although nets or net names are not defined in the probe mapping file or Calibre PERC rule deck, IP cells and other cells/blocks generally have a text file that defines the cell’s pin location (text coordinate), text layers, and pin names. The text layer name or number corresponds to a conductor layer. The probe-mapping file can be created with a cell’s text file and the cell’s coordinate in the top cell.

Figure 2. Coordinate-based P2P check results displayed in Calibre RVE results viewer (Siemens EDA)

Figure 2. Coordinate-based P2P check results displayed in Calibre RVE results viewer (Siemens EDA – click to enlarge)


Device and cell-based P2P and CD checks often require custom rule decks, which can be time-consuming and difficult to create and maintain. Coordinate-based checking significantly minimizes the amount of rule deck changes required, enabling design teams to start P2P/CD verification very quickly, and understand and debug the results easily. In addition to ESD protection verification, P2P/CD checks are applicable to many verification processes, making coordinate-based P2P/CD verification a valuable option for reducing the time and effort required for quick layout checks during early-stage implementation and verification.

For a more detailed discussion of coordinate-based checks, read or download a copy of our technical paper, Enhance IC reliability design verification with coordinate-based P2P and CD checking.


Li Li, Yi-Ting Lee, Sridhar Srinivasan, “Signoff-level full-chip ESD/reliability design verification using logic-driven layout static approach”, IEEE, 2020 China Semiconductor Technology International Conference (CSTIC) https://ieeexplore.ieee.org/document/9282423

About the author

Li Li is a senior foundry product engineer for Calibre Design Solutions at Siemens EDA, supporting Calibre circuit verification and parasitic extraction tools. She has more than 20 years of experience in the EDA and semiconductor industries. Li Li received a B.Sc. from Beijing Jiaotong University.

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