TSMC certifies Aprisa for N5 and N4

By TDF Staff |  No Comments  |  Posted: June 16, 2022
Topics/Categories: Blog - EDA  |  Tags: , , , ,  | Organizations:

TSMC has certified the Aprisa place-and-route software from Siemens Digital Industries Software for the N5 and N4 process technologies.

According to the Aprisa team, the flow needed to pass a rigorous process that exercised the full physical implementation flow with a range of criteria that included DRC, LVS, timing, power, and power-integrity requirements. The Aprisa solution files for N5 and N4 designs are available from TSMC upon customer request.

The certification also follows the recent introduction of a new version of the Aprisa software that offers substantial reductions in both runtime and memory usage. Aprisa uses a unified data model that is shared throughout the entire flow, bringing real route information and parasitics to any engine and any step in the place-and-route flow that is tuned to deliver good results on detailed routes. According to Siemens this approach allows for consistent timing and DRC across engines, which translates to correlation with signoff tools in order to reduce the number of timing ECOs.

In the latest release, announced in October last year, Aprisa achieved an average full-flow runtime reduction of 30 percent compared to the previous release, and up to two-times faster runtimes for larger, more challenging designs. Including optimizations for 6nm, 5nm and 4nm processes, the release made enhancements to all major place-and-route engines, from placement optimization to clock tree synthesis optimization, route optimization and timing analysis. According to Siemens the changes pay off especially on large designs with complicated multi-corner multi-mode (MCMM) features. On these challenging designs, Aprisa has proven to run up to 2X faster than the previous generation.

Other Siemens EDA offerings recently certified for TSMC’s latest processes include the Calibre nmPlatform tool for physical verification, as well as the Analog FastSPICE platform, which designed for nanometer analog, RF, mixed-signal, memory, and custom digital circuits. Both of these Siemens EDA product lines are now certified for TSMC’s advanced N4P and N3E processes. Additionally, as part of the custom design reference flow for TSMC’s N3E process, the Analog FastSPICE platform supports reliability-aware simulation, which includes aging, real-time self-heating effect and advanced reliability features.

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