Mentor tunes LVS for early SoC integration

By Chris Edwards |  No Comments  |  Posted: July 20, 2020
Topics/Categories: Blog - EDA  |  Tags: , , , ,  | Organizations:

Mentor, a Siemens business, has released a tool that attempts to deal with the problems encountered in the use of circuit and layout-versus-schematic (LVS) verification in the early stages of SoC integration.

A common issue in the initial stages of the assembly of large SoCs is that attempting to run conventional LVS verification with an emphasis on sign-off has problems. Hend Wagieh, senior product manager of circuit verification at Mentor, said: “After integration but in the early stages of implementation and assembly, the design will be ‘dirty’. Some blocks will be inserted yet incomplete. DRC is still unclean or fill is not inserted yet. These early or dirty designs can generate millions of errors.”

DRC violations and missing dummy fill polygons are those that designers expect to fix later as the implementation is refined shortly before tapeout. At the same time, others are simple errors such as misidentified nets, poor internal routing, or unexpected shifts in the polygons that affect connections between nets that can and should be corrected as early as possible.

Problem shorts

Shorted nets often cause major issues for sign-off tools because they can generate millions of violations by themselves. “A common comment from design teams is that most of their LVS time is spent on shorted nets. Many times there will be power-ground short: if you highlight the affected path the entire circuit lights up.”

The nmLVS-Recon tool attempts to deal with the problem by using a combination of heuristics and user-selectable options to determine which problems to home in on during early integration instead of running a full collection of sign-off checks. The tool implements four main circuit-verification tasks: isolate shorted paths; soft connection conflicts; electrical rule checks; and circuit-layout comparisons. To improve runtime, the tool focuses on finding the blocks with actual shorts rather than trying to identify all affected sections and can be constrained to only analyze specific layers or types of net, such as power and ground.

According to Mentor, early customer trials yielded 10x tool runtime improvements and a three-fold reduction in memory usage compared to sign-off tools.

Michael Buehler-Garcia, vice president of product management for Calibre at Mentor said: “The early design exploration that the Calibre nmDRC-Recon approach offers has already helped design teams shave hours, and in some customer experiences, even days off their circuit verification times. With Calibre nmLVS-Recon technology, Mentor now offers the same opportunity for total turnaround time reduction in circuit verification.”

Avatar acquisition

In another move in the implementation space, Siemens last week acquired place-and-route specialist Avatar Integrated Systems will the aim of integrating the tools into Mentor’s IC-design portfolio. Built on technologies acquired from ATopTech in 2017, Avatar’s route-centric tools are based on a unified in-memory database that lets individual engines for placement, routing, timing analysis, and clock-tree synthesis invoke each other to perform checks before making decisions. The focus on routing is intended for nanometer process nodes where there are significant constraints on wiring direction and spacing that are controlled by lithography technology.

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