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May 14, 2021
How MaxLinear cut physical verification time with in-design DRC
A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.
Article | Topics:
DFM
,
Digital/analog implementation
,
Verification
| Tags:
design rule check
,
DRC
,
multi patterning
,
physical verification
,
pin assignment
,
place and route
,
via selection
| Organizations:
MaxLinear
,
Siemens EDA
December 18, 2019
On-demand DRC within P&R cuts closure time in half for MaxLinear
Case study describes how RF/AMS specialist used Calibre RealTime Digital within its flow for a high-end DSP SoC.
Article | Topics:
Design to Silicon
,
Blog - EDA
| Tags:
design rule check
,
DFM
,
DRC
,
ECO
,
flooplanning
,
multi patterning
,
place and route
,
via selection
| Organizations:
MaxLinear
,
Siemens EDA
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