The 20nm process is caught between a rock and a hard place. The rock being the solid, cost-effective 28nm process and the hard place being the higher-performance finFET processes named 14nm or 16nm but built on more or less the same routing grid as 20nm.
Although the three-dimensional devices add more cost to the technology, the primary source of expense at this level lies in the lithography. With no EUV on the horizon, double patterning and various computational lithography tweaks remain glued to the menu for almost everything from the active layer through to the first few interconnect layers.
The result is a process where, according to Qualcomm’s vice president of technology Geoffrey Yeap, speaking at last year’s IEDM, the back-end-of-line (BEOL) interconnect for mobile devices hit half the die cost at the original forms of 20nm. At 28nm it was a little north of 40 per cent. It has been quite a surge considering how much the device layer used to account for the lion’s share of the expense of advanced nodes.
At IEDM Yeap said the company had been working with foundry TSMC on trying to cut the immense BEOL cost and bring back the cost as well as performance benefits of shrinking according to Moore’s Law. Qualcomm then went on to describe the process in more detail at the June 2014 VLSI Technology Symposium. One of the key changes tried was to the local-interconnect layer, as well as breaking some old assumptions about the metal-interconnect hierarchy.
Altered design rules
By changing the design rules and working on computational lithography techniques such as source-mask optimization, Qualcomm and TSMC managed to reduce the minimum pitch for a local interconnect layer that could be patterned by one mask instead of two to 80nm – enough to fit the 20nm process.
At IEDM, Yeap claimed around nine critical mask layers were taken out compared to the initial definition of 20nm and 14nm/16nm finFET processes. Things appear to have changed a little. Layout optimization and process improvements have led to the decision to employ three masks for the combined local interconnect layers, with double patterning used on lower metal layers at a pitch of 64nm. To assist density, the team opted for an 80nm pitch on the next set of routing layers that could be performed using the one mask again. According to Qualcomm: “The resulting technology is more cost effective compared to 28nm HKMG processes and is cost-competitive versus 28nm polySiON.”
To avoid coloring problems with the double-patterned 64nm-pitch M1 layer, Qualcomm adopted an approach in which traces from abutting cells could share the same colour – using relaxed 90nm pitch. For yield-sensitive parts of the design, the pitch could be relaxed to 95nm to allow single-color patterning. According to Qualcomm, the double-patterned parts of the design are to be used primarily for maximising the density of the core IP blocks, allowing random logic and routing to use a more relaxed pitch.
In the routing layers, by relaxing the interconnect pitch from 80nm to 90nm, designs experience 10 per cent less wire delay and need fewer buffer insertions. Qualcomm expects to use this in higher-performance cores within an SoC.
As well as providing a platform based on high-k, metal-gate transistors for 20nm, Qualcomm expects the BEOL developments used for the process to speed up the yield ramp for its move to TSMC’s 16nm finFET process – as the two will share the same interconnect characteristics. Qualcomm reckons that the yield-learning process could be accelerated by up to six months.
The combination of design and lithography tweaks yield two-fold increase in a transistor density over the 28nm process, Qualcomm claims.
Co-optimization of design and process are likely to yield further improvements in design density and cost in the era of multiple patterning, and can lead to counterintuitive answers. A number of projects have found that by not trying to squeeze standard cells as much as possible you can improve performance and, in some cases density by taking advantage of higher drive strengths and lower capacitance. Strain has been a major candidate in driving this. Now the interrelationship between litho and design is moving to center stage, as can be seen in our self-aligned double patterning guide and in the literature.
The result is that it is becoming very difficult to predict how costs will move in each process node and, as a result, the tradeoffs involved in using them.
Story updated following publication of VLSI Symposium paper