20nm

October 11, 2012

Is your 20nm process gate-last? Maybe it should be

Modelling work by Gold Standard Simulations indicates that gate-last is the sensible choice at 20nm from a design point of view because of variability problems with gate-first processes.
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October 9, 2012

TSMC updates reference flows for 20nm and CoWoS

TSMC has released two reference flows – one for its 20nm and the other for the form of 3D integration favored by the Taiwanese foundry, chip on wafer on substrate (CoWoS).


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October 9, 2012

Event alert: TSMC Open Innovation Platform

With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.
September 6, 2012

Getting ready for 20nm

Tackling the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
June 5, 2012

DAC2012: Collaboration key to success at 20nm

Foundries can’t hand down design rules on tablets of stone any more - success at 20nm will take close collaboration with customers and tool vendors
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June 1, 2012

DAC 2012: STMicro, Cadence, GlobalFoundries in 20nm AMS claims

The troops will be out in force next week to claim progress on 20nm AMS design flows that take manufacturability into account.
March 15, 2012

CDN Live: Cadence’s Encounter revamp collates innovation

Performance boost claimed from streamlining optimization across synthesis and layout using modeling, novel CTS strategy and 20nm-ready features.
February 29, 2012

Technical Newsletter #1: Common Platform, Samsung, ARM, Cadence

Our first email newsletter previews next month's Common Platform Technology Forum 2012 and features exclusive interviews with senior staff at Samsung, ARM and Cadence Design Systems.

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