DTCO tool aims to squeeze more out of older processes

By Chris Edwards |  No Comments  |  Posted: June 8, 2015
Topics/Categories: Blog - EDA  |  Tags: , , , , , ,  | Organizations:

Gold Standard Simulations (GSS) has launched a tool intended to help fabless chipmakers squeeze more out of existing processes rather than accept the risk and expense of moving to more advanced, finFET-based processes.

Asen Asenov, CEO of GSS, claimed: “FinFETs are both difficult to design and to manufacture and remain an expensive option with an unproven yield track record. This uncertainty is causing the fabless community to think twice before committing to this technology. Many are choosing to stay with more mature technologies and to work on alternate strategies that extract more value in terms of performance, power, and leakage.”

The Enigma tool is designed to support design-technology co-optimization (DTCO), in which actual circuit designs are used to tune device characteristics, process recipes, and design rules. DTCO is becoming increasingly important for deciding on lithographic techniques for sub-20nm processes. But it also has the potential to squeeze more performance and power efficiency by tweaking the characteristics of existing processes.

For example, DTCO has already allowed companies such as Qualcomm to tune the 20nm process the company’s uses at TSMC more to its needs for communications devices.

TCAD automation

Enigma attempts to automate the job of deciding which device characteristics should be altered to support key circuitry, such as SRAM arrays, without forcing fabless companies to have their foundry run a series of test chips with variations in implants and oxide thicknesses as well as different device shapes and then manually derive compact models for further simulation.

To predict the behavior of different recipe choices the GSS DTCO toolchain can use most commercial TCAD simulation software, such as Sentaurus Process from Synopsys, Silvaco’s tools, or the Semulator 3D software developed by Coventor.

“Simulator3D offers interesting possibilities for factoring in process-induced variability because it has the capability to simulate large portion of the chip,” Asenov noted.

The Coventor and GSS teams co-operated on the process-simulation work for a paper, “Accurate Simulation of Transistor-Level Variability for the Purposes of TCAD-Based Device-Technology Cooptimization“, published in June’s IEEE Transactions on Electron Devices that analyzed the impacts of manufacturability and variability on a finFET process.

The Enigma tool coordinates the software environment, automating the job of running and storing the results of multiple TCAD simulations using a design-of-experiments approach. According to the company, this may be on the scale of thousands of different options, including global and local variability and reliability.

Enigma then extracts compact models before running simulations on critical testbench circuits and delivering results that may show that a given experiment delivers less leakage from an SRAM than others with no impact on the performance.

“For fabless customers, who do not have access to the detailed process flow [from their foundry] we offer reverse engineering facilities which reconstruct the doping distribution based on comprehensive sets of electrical measurements. Then the DTCO is based on the reverse engineered structure,” Asenov explained.

CSR’s senior director of process development, David Vigar, said: “We have worked with GSS on process optimization and found the results to be in line with the silicon results.”

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