June 5, 2013
The increasing use of graphics in mobile SoCs means that finFET processes need to be optimised for density and power - as well as early availability at low risk.
March 20, 2013
EDA companies are having to plan for the different ways in which double patterning and finFETs could move into fabs, Antun Domic of Synopsys explains.
March 20, 2013
An early shift to finFET processes is making developing IP libraries more challenging.
January 28, 2013
Cadence Design Systems has built into its latest Virtuoso update features designed to tackle the problems of working with the 20nm generation of processes with finer control over layout-dependent effects, double patterning and new types of local interconnect.
December 4, 2012
20nm design is fraught with problems for analog design but one that causes the biggest headaches is density variation, says Synopsys' Joachim Kunkel.
December 4, 2012
finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
October 26, 2012
The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
October 16, 2012
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
October 11, 2012
Intel finFET family grows to support SoC use, as TSMC boosts p-channel performance with germanium
October 11, 2012
Manufacturability, routing, library design and more - it all needs rethinking at 20nm