20nm

June 5, 2013

FinFET processes demand delicate tradeoffs for mobile SoCs – GlobalFoundries process architect

The increasing use of graphics in mobile SoCs means that finFET processes need to be optimised for density and power - as well as early availability at low risk.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations:
March 20, 2013

DATE: Double patterning and finFETs force flexibility on tools

EDA companies are having to plan for the different ways in which double patterning and finFETs could move into fabs, Antun Domic of Synopsys explains.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
March 20, 2013

DATE: Early shift to finFET processes challenges IP development strategies

An early shift to finFET processes is making developing IP libraries more challenging.
Article  |  Topics: Conferences, Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations:
January 28, 2013

Cadence updates Virtuoso for the 20nm generation

Cadence Design Systems has built into its latest Virtuoso update features designed to tackle the problems of working with the 20nm generation of processes with finer control over layout-dependent effects, double patterning and new types of local interconnect.
December 4, 2012

IPSoC: 20nm causes analog ‘density fill headaches’

20nm design is fraught with problems for analog design but one that causes the biggest headaches is density variation, says Synopsys' Joachim Kunkel.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
December 4, 2012

FinFET tipsheet for IEDM

finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
October 26, 2012

Mentor Graphics CEO Wally Rhines – Interview

The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
October 16, 2012

EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes

IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
October 11, 2012

Intel, TSMC finFETs to star at IEDM

Intel finFET family grows to support SoC use, as TSMC boosts p-channel performance with germanium
Article  |  Topics: Blog Topics, Commentary, Blog - EDA  |  Tags: , , , ,   |  Organizations: , ,
October 11, 2012

The physical design challenges of 20nm processes

Manufacturability, routing, library design and more - it all needs rethinking at 20nm
Article  |  Topics: Design to Silicon, Blog - EDA, - Industry Blogs  |  Tags: , , , ,   |  Organizations:

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