French research group CEA-Leti expects to have design kits ready for a 10nm fully depleted silicon-on-insulator (FD-SOI) process in June 2014, Jean-René Lequepeys, vice president of the silicon components division told Future Horizons’ International Electronics Forum in Dublin today (4 October 2014).
Lequepeys told delegates that a shift to a new device architecture would probably be needed at or after the 7nm node to a nanowire device structure. “We can add strain and germanium to the channel for higher performance,” he said. “And we also add on top what we call monolithic 3D, where we put transistors on top of transistors. We can use different materials in the two sections.”
Beyond 5nm, Lequepeys said a mechanical switch is under consideration.
Because of the tradeoffs that will be needed for the sub-10nm processes, Lequepeys said: “We will need very tight integration between the process team and design team.”
There are questions as to what “10nm” represents with regards to the effective density of the process. The 14nm FD-SOI process planned by STMicroelectronics for which the design kit was released last quarter has transistor and interconnect dimensions that would normally be associated with a 20nm process.
On Thursday, Future Horizons president Malcolm Penn called for an end for the current numbers war in the sub-20nm processes. An analysis performed by Future Horizons CTO Mike Bryant using SRAM density as a proxy for the scaling changes of the latest crop of processes indicated that none of the “14nm” processes use inter-transistor spacings that the industry’s roadmap proposed. The two major foundries’ finFET processes are already known to use the 20nm process dimensions for interconnect, replacing the planar transistor with the 3D transistor structure.
“We would put Intel at between 16 and 17nm. Samsung is at 18nm. TSMC and GlobalFoundries are at 20nm. ST is at 21nm,” said Penn.