Gold Standard Simulations


June 8, 2015

DTCO tool aims to squeeze more out of older processes

Gold Standard Simulations (GSS) has launched a tool intended to help fabless chipmakers squeeze more out of existing processes rather than accept the risk and expense of moving to more advanced, finFET-based processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
May 25, 2015

Shape a major choice for sub-10nm nanowire FETs

TCAD specialist GSS says nanowire transistors look practical down to 5nm but that designers need to carefully explore how the wires are shaped as quantum-confinement effects take hold
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
August 19, 2014

Simulations point to better performance for Intel 14nm finFET

Gold Standard Simulations has run simulations to work out how much of an improvement Intel's new rectangular shape represents.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: ,
July 25, 2014

GlobalFoundries licenses atomistic TCAD simulator toolchain

Foundry licenses atomistic TCAD simulator to better understand key aspects of advanced process nodes.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: ,
October 11, 2012

Is your 20nm process gate-last? Maybe it should be

Modelling work by Gold Standard Simulations indicates that gate-last is the sensible choice at 20nm from a design point of view because of variability problems with gate-first processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
May 14, 2012

Intel’s tapered fin reveals short-channel issues

A startup has analyzed the shape of Intel's fins and found the process is not quite as well-behaved as circuit designers would perhaps like.
Article  |  Topics: Commentary, Design to Silicon  |  Tags: , ,   |  Organizations: ,

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