local interconnect


January 7, 2015

CEA-Leti deals with heat issue on monolithic 3DIC

At IEDM 2014, CEA-Leti presented a technique that prevents damage to base-layer transistors in monolithic 3DIC processes. As work progresses, the institute is preparing to receive 3DIC designs in 2017.
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June 3, 2014

Remember 20nm? Qualcomm does

Qualcomm will present at VLSI Technology Symposium 2014 a version of TSMC's 20nm technology that uses design and process tweaks to reduce the number of double-patterned layers.
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January 28, 2013

Cadence updates Virtuoso for the 20nm generation

Cadence Design Systems has built into its latest Virtuoso update features designed to tackle the problems of working with the 20nm generation of processes with finer control over layout-dependent effects, double patterning and new types of local interconnect.

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