Electrically aware Virtuoso aims to head off physical issues

Cadence Design Systems has rolled out a new version of Virtuoso that is intended to deal with the increasing number of physical-implementation issues that arise in the sub-28nm nodes. Virtuoso Electrically Aware Design (EAD) reduces the number of full circuit-design iterations and combats the temptation to overdesign parts of the circuit in attempts to head off these physical issues.

In January this year, Cadence introduced a version of Virtuoso that provides a more iterative approach to laying out analog circuits so that designers could get a grip on electrical issues much earlier, rather than wait until the layout is completed before verifying that it meets the original design intent. That release focused on device-level issues such as stress, which can greatly affect the performance of individual transistors.

The performance of sub-40nm transistors often depends on placement – whether the device is close to a well edge or surrounded by similar transistors. If you need to have dummy transistors sitting alongside a critical component, you probably want to know about that before you have a fully placed and routed design to avoid having to rip it up and start again.

The latest update extends the range of tasks that can be done before the full layout is ready. There is an interconnect parasitic extraction engine that evaluates layout as it is created and provides an in-design electrical view for real-time analysis and optimization. There is also electromigration (EM) analysis that alerts layout engineers to any EM issues that are being created as the layout is drawn.

In tests with early-access customers, Cadence reckons Virtuoso Layout Suite EAD lets engineers cut their circuit design cycle time by up to 30 per cent this way.

The suite provides the ability to capture currents and voltages from simulations run in the Virtuoso Analog Design Environment, and pass that electrical information forward into the layout environment. It also provides for a greater level of collaboration between circuit designers and layout designers to achieve electrically correct-by-construction layout.