FD-SOI vs finFETs mulled during IEDM

By Luke Collins |  1 Comment  |  Posted: December 11, 2012
Topics/Categories: Conferences, Design to Silicon, Blog - EDA  |  Tags: , , , , , , , ,  | Organizations: , , , , , ,

The SOI lobby was out in force at Monday night’s IEDM, presenting a roadmap from bulk CMOS to planar devices on fully-depleted SOI (Guide) and then to finFETs (Guide) on oxide as the natural way forward for process developers moving below 20nm minimum dimensions.

Joel Hartmann, executive vice president of front-end manufacturing and process R&D at STMicroelectronics, told the crowd at the Fully Depleted Transistors Technology Symposium put on by the SOI Industry Consortium that “at 20nm we have reached the limits of bulk planar silicon.”

“FD-SOI is faster than bulk, faster than the current finFET technology, cooler in terms of offering less leakage; easier to design with; and simpler, because porting from bulk is simple.”

If that doesn’t convince, he also offered a ‘get out of jail free’ card – the FD-SOI process that has been developed jointly by STMicroelectronics, CEA-LETI and IBM allows you to build on bulk if you want to by etching through the carefully prepared ultrathin active silicon layer and the underlying buried oxide into the bulk. Apparently, it’s a handy way of building ESD protection at the moment without having to completely rethink your approach to work on FD-SOI.

Hartmann claimed that circuits built on FD-SOI could run 30% faster, or offer 50% greater energy efficiency than the same circuits running on bulk. He also praised the technology’s ability to support back biasing, which allows designers to manipulate threshold voltages – by up to 85mV for each volt of bias, compared with a claimed 25mV/V for bulk.

The cost issue was also tackled. The argument is that the extra cost of SOI wafers is offset by cost savings made because you no longer need to dope the channels. The net effect is that although you add mask steps to pattern a raised source and drain, and to reveal the bulk silicon if necessary, the overall number of mask steps falls from 42 to 36.

“You can totally absorb the extra cost of the start wafer,” said Hartmann. “We don’t want this to be a boutique technology for ST only.”

FD-SOI ready for production

Backing up this position he said that the company’s 28nm UTBB SOI process is now available for production designs, that it is qualified with SOI wafers from three sources, and that GlobalFoundries is lined up as a volume production partner. The lack of channel dopants, Hartmann argued, should also lead to reduced process variability and therefore faster yield learning. Models and a PDK are available, as is a silicon-qualified IP library ported across from the bulk libraries.

ST has proven the process by producing a NovaThor ModAp (modem/applications) processor for ST-Ericcson in the technology, using multiple ARM A9 cores. It expects the part to run 30% faster or at 30% lower power than the same thing on bulk. The moment was only slightly spoiled by STMicroelectronics reconfirming on Monday morning that it was withdrawing from the ST- Ericsson partnership.

Hartmann preferred to focus on the future of the process. With minimum gate dimensions no longer as meaningful in defining process density as they used to be, STMicroelectronics has gone with the flow and redefined its next process node, built using 20nm design rules, as a 14nm process, in much the same way as Intel has named its small finFET/large design rules approach a 22nm trigate process.

With that out of the way, Hartmann said “we know we will be able to go to 14nm and 10nm by shrinking the silicon thickness and the buried oxide thickness.” The 14nm FD-SOI process may get a SiGe channel for the pFET and in-situ doping for the raised source/drain area. The thinner buried oxide layer is also expected to improve body bias efficiency, to 150mV/V.

Overall performance improvement claims for the shift from 28nm to 14nm include 30% greater peak speed or 30% lower power operation. The shift from 14nm to 10nm is expected to bring a 25% speed bump.

Body bias for better FPGAs?

Jeff Watt, technology development Fellow at Altera, has been experimenting with models for the 28nm FD-SOI process, provided by the SOI Consortium and backed by experimental silicon results from IBM, to understand the value of FD-SOI to FPGA makers.

One aspect where the two fit well is in supporting Altera’s ‘programmable power technology’ strategy, which uses body biasing to adjust the power/performance trade-off of the process to match the local needs of the user’s design. Blocks that are among the 20% of the user’s design that is on the critical path when programmed on to the Altera array are forward-biased for performance, while other active blocks that are off  the critical path get a reverse body bias to reduce leakage. Inactive blocks are turned off using clock gating.

Watt said that his simulations had shown a 35% speed improvement moving from 28nm bulk to 14nm FD-SOI, or a 325 reduction in power at the same speed. He also praised the process’s ability to modulate body bias over a wide range, rather than the few millivolts possible in a bulk process. He said this meant you could achieve a 30% reduction in Off current in bulk, but a 90% reduction in FD SOI. The body bias range is also helpful in enabling designers to tune out the effects of process variations.

FinFET myths exploded

Ed Nowak, IBM Distinguished Engineer and Device Chief Designer at the Semiconductor R&D Center of IBM Systems and Technology Group, set out to compare and contrast various approaches to next generation processes, from bulk to partially depleted SOI to planar full depletion, bulk finFETs and finally finFETs on oxide.

Both planar FD-SOI and finFETs offer good short channel control, and the planar devices also add the back biasing that Altera finds so useful – although the planar device’s scalability may ultimately be limited by their body thickness. FinFETs, on the other hand, although demanding more complex processing, are electrically wider than their physical footprint and offer better scalability. Fins on oxide are simpler to make, taking three process steps before you start on the business of actually patterning feature such as source/drain contacts, while a fin on bulk takes seven steps to get to the same stage, with the extra steps being used to drive in some isolation between the fin and the bulk. This bulk isolation takes a lot of doping to be as effective as building on oxide, which compromises drive current and drives up the minimum operating voltage for the device, because the doping variability means you need more headroom to ensure SRAM performance is unaffected.

Nowak also set out to demolish four myths about fins on oxide: first, they don’t get undercut when over-etched and fall over, in his experience; second, although you can strain a fin on bulk by perhaps 15% than a fin on oxide, this might give a 5% improvement in drive current and a 0 to 2% performance gain; third, self heating happens for all fins, and although fins on bulk have a better way of dissipating that heat, it doesn’t really matter for standard CMOS circuits at usual activity levels, though it may have an impact for high-speed I/Os and high-duty clock drivers; and fourth, you can build passives on SOI, or just etch through the buried oxide and work in the underlying bulk.

Advantages of the fin on oxide approach include its amenability to establishing voltage islands, the ease with which high-voltage devices can be built, its superior RF performance and its ability to host on-chip embedded DRAM, at three times the density of embedded SRAM.

Nowak predicted that the fin on oxide approach could take the industry through to what he thinks may be a fundamental scaling limit at minimum feature sizes of 3 to 5nm – but he pointed out that when the industry has been unable to scale its whole process linearly in the past it has still scaled individual elements to achieve further performance gains.

FD-SOi vs finFET trade-offs

Rob Aitken, ARM Fellow, rounded up the proceedings by asking the audience to work with him to compare the features and benefits of planar FD-SOI and bulk finFETs.

For chip designers, protected by the abstraction of the cell library, there’s no advantage either way in terms of ease of design.

For leakage control, FD-SOI wins.

For dynamic power mitigation, voltage scaling is probably better with the finFET.

In terms of supply chain, the bulk finFET wins.

For density, the finFET’s design may give it a slight advantage, although difficulties in contacting the fin may make it marginal.

For manufacturability, the FD-SOI device wins based on existing use of SOI.

For performance, finFETs have more channel, which is good, but their discrete device sizing can prove a design headache.

For design portability, Aitken said that as an ARM employee who spends a lot of time porting designs, his view is “nothing ports anywhere, ever”, but in this case he would give the advantage to FD-SOI for its closeness to the bulk process. For finFETs, he added, you can’t even port schematics to them – it takes a design rethink.

For SRAM support, bit cells are limited in a fin world and so FD-SOI wins on flexbibility.

For analogue support, the discrete device sizes of finFETs limit analogue design option in theory, although Aitken say that in practice most devices are so big that it doesn’t really matter whether you build them with, for example, 106 or 107 fins rather than an optimal 106.5.

For future scaling, Aitken gave the advantage to the finFET.

Horacio Mendez, executive director of the SOI Industry Consortium, concluded by saying that moving to FD planar devices is a step on the road to the use of finFETs, either on bulk or eventually on oxide.

“For today, a planar FD approach gives better time to market at lower risk.”

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